参数资料
型号: SP6655ER-L/TR
厂商: Exar Corporation
文件页数: 10/17页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.4A 10DFN
标准包装: 3,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1 V ~ 5 V
输入电压: 2.7 V ~ 5.5 V
电流 - 输出: 400mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-VFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 10-DFN(3x3)
S P 6 6 5 5
H i g h E f f i c i e n c y 4 0 0 m A S y n c h r o n o u s B u c k R e g u l a t o r
period. This blanking period occurs during the
noisy LX transition to discharge, where
spurious comparator states may occur. For
T OFF > T BLANK , the loop is in a discharge or wait
state until the loop comparator starts the next
charge cycle by DRVON going high.
If an over current condition occurs during
charge, the loop is interrupted and DRVON is
RESET. The off-time one-shot pulse width is
widened to T OFF = K OFF / V OUT , which holds the
loop in discharge for that time. At the end of
If the I OUT * R CH term is negligible compared
with (V IN - V OUT ), the above equation simplifies
to:
For most applications, the inductor current
ripple controlled by the SP6655 is constant
regardless of input and output voltage.
The maximum loop frequency in CCM is
defined by the equation:
the off-time,
the loop is released
and
controlled by VOLOW. In this manner
maximum inductor current is controlled on a
cycle-by-cycle basis. An assertion of UVLO
(undervoltage lockout) or TSD (thermal
shutdown) holds the loop in no-charge until
the fault has ended.
O N -T IME C ONTROL - D ISCHARGE P HASE
The discharge phase follows with the high side
PMOS switch opening and the low side NMOS
switch closing to provide a discharge path for
the inductor current. The decreasing inductor
current and the load current cause the output
voltage to drop. Under normal load conditions
when the inductor current is below the
programmed limit, the off-time will continue
until the output voltage falls below the
regulation threshold, which initiates a new
charge cycle via the loop comparator.
The inductor current “floats” in continuous
conduction mode. During this mode the
inductor peak current is below the
programmed limit and the valley current is
above zero. This is to satisfy load currents that
are greater than half the minimum current
ripple. The current ripple, I LR , is defined by the
equation:
where:
L = Inductor value
I OUT = Load current
R CH = PMOS on resistance, 0.3 Ωtyp.
where:
F LP = CCM loop frequency
R DC = NMOS on resistance, 0.3 Ωtyp.
Ignoring conduction losses simplifies the loop
frequency to:
AND’ing the loop comparator and the on -timer
reduces the switching frequency for load
currents below half the inductor ripple current.
This increases light load efficiency. The
minimum on-time insures that the inductor
current ripple is a minimum of K ON /L, more
than the load current demands. The converter
goes in to a standard pulse frequency
modulation (PFM) mode where the switching
frequency is proportional to the load current.
L OW D ROPOUT AND L OAD T RANSIENT
O PERATION
AND’ing the loop comparator also increases
the duty ratio past the ideal D= V OUT /V IN up to
and including 100%. Under a light to heavy
load transient, the loop comparator will hold
the main switch on longer than the minimum
on timer until the output is brought back into
regulation.
Also, as the input voltage supply drops down
close to the output voltage, the main MOSFET
resistance loss will dictate a much higher duty
ratio to regulate the output. Eventually as the
input voltage drops low enough, the output
voltage will follow, causing
the loop
? 2012 Exar Corporation
10/17
Rev. 1.0.0
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