参数资料
型号: SP708CN-L/TR
厂商: Exar Corporation
文件页数: 10/17页
文件大小: 0K
描述: IC MPU SUPERVISORY CIRCUIT 8SOIC
标准包装: 2,500
类型: 简单复位/加电复位
监视电压数目: 1
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.4V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
S P 7 0 5 - S P 7 0 8 - S P 8 1 3 L
L o w P o w e r M i c r o p r o c e s s o r S u p e r v i s o r y C i r c u i t s
Fig. 18: SP705/706/813L Watchdog Timing Waveforms
Fig. 20: Typical Operating Circuit
M ANUAL R ESET
The manual-reset input ( MR ) allows RESET to
be triggered by a pushbutton switch. The
switch is effectively debounced by the 140ms
minimum RESET pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by an
Fig. 19: SP705/706 Timing Diagrams with WDI tri-stated.
P OWER -F AIL C OMPARATOR
The power-fail comparator can be used for
various purposes because its output and non
inverting input are not internally connected.
The inverting input is internally connected to a
1.25V reference.
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in Figure 20. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator
drops out. Use PFO to interrupt the μP so it
can prepare for an orderly power-down.
external logic line. MR can be used to force a
watchdog timeout to generate a RESET pulse
in the SP705/706/813L. Simply connect WDO
to MR .
Ensuring a Valid Reset Output Down to
V CC =0V
When V CC falls below 1.1V, the
SP705/706/707/708 RESET output no longer
sinks current, it becomes an open circuit.
High-impedance CMOS logic inputs can drift to
undetermined voltages if left undriven. If a
pull-down resistor is added to the RESET pin,
any stray charge or leakage currents will be
shunted to ground, holding RESET LOW. The
resistor value is not critical. It should be about
100KW, large enough not to load RESET and
small enough to pull RESET to ground.
? 2010 Exar Corporation
10/17
Rev. 2.0.0
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