参数资料
型号: SP708SCN-L
厂商: Exar Corporation
文件页数: 11/16页
文件大小: 0K
描述: IC MPU SUPERVISORY CIRCUIT 8SOIC
标准包装: 98
类型: 简单复位/加电复位
监视电压数目: 1
复位: 高有效/低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.93V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 管件
其它名称: 1016-1534-5
SP708SCN-L-ND
S P 7 0 6 R / S / T - S P 7 0 8 R / S / T
3 . 0 V / 3 . 3 V L o w P o w e r M i c r o p r o c e s s o r S u p e r v i s o r y
C i r c u i t s
M ANUAL R ESET
The manual-reset input ( MR ) allows RESET to
be triggered by a pushbutton switch. The
switch is effectively debounced by the 140ms
minimum RESET pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by an
external logic line. MR can be used to force a
watchdog timeout to generate a RESET pulse
in the SP706R/S/T-SP708R/S/T. Simply
connect WDO to MR .
Ensuring a Valid Reset Output Down to
V CC =0V
Fig. 19: Timing Diagrams with WDI tri-stated.
P OWER -F AIL C OMPARATOR
The power-fail comparator can be used for
various purposes because its output and non
inverting input are not internally connected.
The inverting input is internally connected to a
1.25V reference.
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in Figure 20. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator
drops out. Use PFO to interrupt the μP so it
can prepare for an orderly power-down.
Fig. 20: Typical Operating Circuit
When V CC falls below 1V, the RESET output no
longer sinks current, it becomes an open
circuit. High-impedance CMOS logic inputs can
drift to undetermined voltages if left undriven.
If a pull-down resistor is added to the RESET
pin, any stray charge or leakage currents will
be shunted to ground, holding RESET LOW.
The resistor value is not critical. It should be
about 100K ? , large enough not to load RESET
and small enough to pull RESET to ground.
M ONITORING V OLTAGES O THER THAN THE
U NREGULATED DC I NPUT
Monitor voltages other than the unregulated
DC by connecting a voltage divider to PFI and
adjusting the ratio appropriately. If required,
add hysteresis by connecting a resistor (with a
value approximately 10 times the sum of the
two resistors in the potential divider network)
between PFI and PFO . A capacitor between PFI
and GND will reduce the power-fail circuit's
sensitivity to high-frequency noise on the line
being monitored. RESET can be used to
monitor voltages other than the +3.3V/+3.0V
V CC line. Connect PFO to MR to initiate a
RESET pulse when PFI drops below 1.25V.
Figure 21 shows the SP706R/S/T-SP708R/S/T
series configured to assert RESET when the
+3.3V/3.0V supply falls below the RESET
threshold, or when the +12V supply falls
below approximately 11V.
M ONITORING A N EGATIVE V OLTAGE S UPPLY
The power-fail comparator can also monitor a
negative supply rail, shown in Figure 22. When
the negative rail is good (a negative voltage of
large magnitude), PFO is LOW. By adding the
? 2010 Exar Corporation
11/16
Rev. 2.0.0
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