参数资料
型号: SP721ABT
厂商: Littelfuse Inc
文件页数: 6/6页
文件大小: 0K
描述: TVS ARRAY ESD 6 INPUT 8-SOIC
标准包装: 2,500
系列: SP721
电压 - 工作: 30V
技术: 混合技术
电路数: 6
应用: 通用
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
TVS Diode Arrays
Electronic Protection Array for ESD and Overvoltage Protection
SP721
Small Outline Plastic Packages (SOIC)
M8.15
(JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
E
-B-
H
0.25(0.010) M
B M
SYMBOL
A
INCHES
MIN MAX
0.0532
0.0688
MILLIMETERS
MIN MAX
1.35
1.75
NOTES
-
A1
0.0040
0.0098
0.10
0.25
-
1
2
3
L
B
0.013
0.020
0.33
0.51
9
SEATING PLANE
C
0.0075
0.0098
0.19
0.25
-
-A-
D
A
h x 45 o
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
-C-
e
0.050 BSC
1.27 BSC
-
e
B
0.25(0.010) M
C A M
B S
A1
μ
0.10(0.004)
C
H
h
L
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
5
6
N
8
8
7
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
μ
0 o
8 o
0 o
8 o
-
5
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
w w w. l i t t e l f u s e . c o m
239
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