参数资料
型号: SP7652EB
厂商: Exar Corporation
文件页数: 8/15页
文件大小: 0K
描述: EVAL BOARD FOR SP7652
标准包装: 1
系列: *
S P 7 6 5 2
P o w e r b l o x T M
6 A 2 8 V 6 0 0 K H z S y n c h r o n o u s S t e p D o w n R e g u l a t o r
reference, a short-circuit fault is set. Because
the SS pin overrides the internal 0.8V
reference during soft start, the SP7652 is
or the SS pin has exceeded 1.7V. This feature
prevents the controller from “dragging down”
the output voltage during startup or in fault
capable of detecting short-circuit
faults
modes. The second feature is a 100% duty
throughout the duration of soft start as well as
in regular operation.
H ANDLING OF F AULTS
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7652 is forced
into an idle state where the SS and COMP pins
are pulled low and the NFETS are held off. In
the event of UVLO fault, the SP7652 remains
in this idle state until the UVLO fault is
removed. Upon the detection of a thermal or
short-circuit fault, an internal 200ms timer is
activated. In the event of a short-circuit fault,
a re-start is attempted immediately after the
200ms timeout expires. Whereas, when a
thermal fault is detected, the 200ms delay
continuously recycles and a re-start cannot be
attempted until the thermal fault is removed
and the timer expires.
E RROR A MPLIFIER AND V OLTAGE L OOP
Since the heart of the SP7652 voltage error
loop is a high performance, wide bandwidth
transconductance amplifier, great care should
be taken to select the optimal compensation
network. Because of the amplifier’s current
limited (±150μA) transconductance, there are
many ways to compensate the voltage loop or
to control the COMP pin externally. If a simple,
single-pole, single-zero response is desired,
then compensation can be as simple as an RC
circuit to Ground. If a more complex
compensation is required, then the amplifier
has enough bandwidth (45°C at 4MHz) and
enough gain (60dB) to run Type III
compensation schemes with adequate gain
and phase margins at cross over frequencies
greater than 50kHz.
The common mode output of the error
amplifier is 0.9V to 2.2V. Therefore, the PWM
voltage ramp has been set between 1.1V and
2.2V to ensure proper 0% to 100% duty cycle
capability. The voltage loop also includes two
other very important features. One is an
asynchronous startup mode. Basically, the
synchronous rectifier cannot turn on unless
the high-side NFET has attempted to turn on
cycle timeout that ensures synchronized
refreshing of the BST capacitor at very high
duty ratios. In the event that the high-side
NFET is on for 20 continuous clock cycles, a
reset is given to the PWM flip-flop half way
through the 21st cycle. This forces GL to rise
for the cycle, in turn refreshing the BST
capacitor.
P OWER MOSFET S
The SP7652 contains a pair of integrated low
resistance N-MOSFETs designed to drive up to
6A of output current. Maximum output current
could be limited by thermal limitations of a
particular application. The SP7652
incorporates a built-in over-temperature
protection to prevent internal overheating.
S ETTING O UTPUT V OLTAGES
The SP7652 can be set to different output
voltages. The relationship in the following
formula is based on a voltage divider from the
output to the feedback pin V FB , which is set to
an internal reference voltage of 0.80V.
? 2012 Exar Corporation
8/15
Rev. 2.0.0
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