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| 型号： | SP7652ER-L |
| 厂商： | Exar Corporation |
| 文件页数： | 12/15页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A 26DFN |
| 标准包装： | 500 |
| 系列： | Power Blox™ |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 27 V |
| 输入电压： | 2.5 V ~ 28 V |
| PWM 型： | 电压模式 |
| 频率 - 开关： | 600kHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 26-VFDFN 裸露焊盘 |
| 包装： | 散装 |
| 供应商设备封装： | 26-DFN（7x4） |
| 其它名称： | 1016-1537-5 SP7652ER-L-ND |
S P 7 6 5 2
P o w e r b l o x T M
6 A 2 8 V 6 0 0 K H z S y n c h r o n o u s S t e p D o w n R e g u l a t o r
Definitions:
R ESR = Output Capacitor Equivalent Series Resistance
R DC = Output Inductor DC Resistance
R RAMP_PP = SP7652 internal Ramp Amplitude Peak to Peak Voltage
Conditions:
C Z 2 >> Cp1 and R1 >> R Z 3
Output Load Resistance >> RESR and RDC
Fig. 14: Type III Error Amplifier Compensation Circuit
Fig. 13: Bode Plot of Type III Error Amplifier Compensation
SP765X T HERMAL R ESISTANCE
The SP765X family has been tested with a
variety of footprint layouts along with
different copper area and thermal resistance
has been measured. The layouts were done
on 4 layer FR4 PCB with the top and bottom
layers using 3oz copper and the power and
ground layers using 1oz copper.
For the Minimum footprint, only about 0.1
square inch (of 3 ounces of) Copper was used
on the top or footprint layer, and this layer
had no vias to connect to the 3 other layers.
For the Medium footprint, about 0.7 square
inches (of 3 ounces of) Copper was used on
the top layer, but vias were used to connect
to the other 3 layers. For the Maximum
footprint, about .0 square inch (of 3 ounces
of) Copper was used on the top layer and
many vias were used to connect to the 3
other layers.
The results show that only about 0.7 square
inches (of 3 ounces of) Copper on the top
layer and vias connecting to the 3 other
layers are needed to get the best thermal
resistance of 36°C/W. Adding area on the top
beyond the 0.7 square inches did not reduce
thermal resistance.
Using a minimum of 0.1 square inches of (3
ounces of) Copper on the top layer with no
vias connecting to the 3 other layers
produced a thermal resistance of 44°C/W.
This thermal impedance is only 22% higher
than the medium and large footprint layouts,
indicating that space constrained designs can
still benefit thermally from the Powerblox
family of ICs. This indicates that a minimum
footprint of 0.1 square inch, if used on a 4
layer board, can produce 44°C/W thermal
resistance. This approach is still very
worthwhile if used in a space constrained
design.
? 2012 Exar Corporation
12/15
Rev. 2.0.0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SP7652ERL/TR | 制造商:SIPEX 制造商全称:Sipex Corporation 功能描述:Wide Input Voltage Range 6A, 600kHz, Buck Regulator |
| SP7652ER-L/TR | 功能描述:电压模式 PWM 控制器 WIDE INPUT VOLTAGE RANGE, 3A 600k RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| SP7652EU | 制造商:SIPEX 制造商全称:Sipex Corporation 功能描述:Evaluation Board Manual |
| SP7653 | 制造商:SIPEX 制造商全称:Sipex Corporation 功能描述:Wide Input Voltage Range, 1.3MHz, Buck Regulator |
| SP7653_06 | 制造商:SIPEX 制造商全称:Sipex Corporation 功能描述:Wide Input Voltage Range, 1.3MHz, Buck Regulator |
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