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参数资料
| 型号： | SP8660ACM |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 谐振器 |
| 英文描述： | 8600 SERIES, PRESCALER, MBCY8 |
| 封装： | METAL CAN-8 |
| 文件页数： | 4/6页 |
| 文件大小： | 175K |
| 代理商： | SP8660ACM |
3
SP8660A
OPERATING NOTES
1.The clock inputs (pins 1 and 8) should be capacitively coupled
to the signal source. When driven single ended, the input signal
path is completed by a capacitor from the unused input to ground.
2. In the absence of a signal the devices will self-oscillate. This can
be prevented by connecting a 39k
resistor from either input to
ground. If the device is driven single ended, it is recommended
that the pull-down resistor be connected to the decoupled unused
input. There will be a loss in sensitivity of approximately 200mV.
3. The device will operate down to DC but input slew rate must be
better than 100V/
s.
4. The open collector output will drive three TTL loads, and
therefore requires a a suitable resistor to VCC to maintain noise
immunity. In order to maintain noise immunity on transitions, this
resistor should not exceed 47k
. For interfacing to CMOS, the
open collector may be restored to a 110V line via a 33k
resistor.
The output sink current must not exceed 10mA and the use of too
low a value of resistor may lead to a loss of noise immunity,
especially at low temperatures.
5. Input impedance varies as a function of frequency; see Fig. 4.
6. The rise time of the open collector output waveform is directly
proportional to the load capacitance and load resistor value.
Therefore, the load capacitance should be minimised and the
load resistor kept to a minimum compatible with system power
requirements.
In the test configuration of Fig. 5, the output rise time is
approximately 20ns and the fall time is typically 10ns.
DUT
1k
100n
SAMPLING
SCOPE
INPUT
4
8
1n
FROM
GENERATOR
TO SAMPLING
SCOPE
5
1n
VCC
2
10n
7p
1
1
10V
33k
Fig. 5 Test circuit
Fig. 6. Typical application circuit showing interfacing
4
5
16k
1
8
2
BIAS
CMOS
33k
39k
1n
1
5V
INPUT
16k
DIVIDE BY
10
1
5V/110V
(DEPENDING ON
CMOS SUPPLY VOLTAGE)
SP8660
4
2
1
5V
22k
TTL
Fig. 7. Interfacing to TTL. Load not to exceed 3 TTL unit loads
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SP8660DP | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:150MHz±10 Low Power ECL Counter |
| SP8665B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:The SP8865/8 are asynchronous ECL counters which provide ECL compatible outputs |
| SP8668B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:The SP8865/8 are asynchronous ECL counters which provide ECL compatible outputs |
| SP8680 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:575-MHz-Vorteilerschaltkreis mit Teilerfaktor 10 oder 11 |
| SP8685A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:500MHz ± 10/11 ECL Variable Modulus Divider |
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