参数资料
型号: SP8685BDG
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 谐振器
英文描述: 8685 SERIES, PRESCALER, CDIP16
封装: CERAMIC, DIP-16
文件页数: 4/8页
文件大小: 185K
代理商: SP8685BDG
3
SP8685
OPERATING NOTES
1. The clock input is biased internally and is coupled to the signal
source with a suitable capacitor. The input signal path is completed
by an input reference decoupling capacitor which is connected
from pin 10 to ground.
2. If no signal is present the device will self-oscillate. If this is
undesirable, it may be prevented by connecting a 15k
resistor
from the clock input (pin 12) to VEE. This will reduce the input
sensitivity by approximately 100mV.
3. The circuit will operate down to DC but slew rate must be better
than 100V/
s.
4. The outputs are compatible with ECLII but can be interfaced to
ECL10K as shown in Fig. 7.
5. The PE inputs are ECLIII/10K compatible and include 43k
pulldown resistors. Unused inputs can therefore be left open.
6. Input impedance is a function of frequency, See Fig. 5.
7. All components should be suitable for the frequency in use.
Fig. 5 Typical input impedance. Test conditions: Supply Voltage = 252V,
Ambient Temperature = 25
°C. Frequencies in MHz, impedances normalised to 50.
DUT
450
0.1
0.1
OUTPUTS TO
SAMPLING
SCOPE
VEE
16
2
4
8
10
12
1n
33
20
INPUT FROM
GENERATOR
TO SAMPLING
SCOPE
Fig. 6 Test circuit
j 2
j 1
j 0.5
j 0.2
0
2
j 0.2
2
j 0.5
2
j 1
2
j 2
1
0.5
0.2
j 5
2
j 5
2
5
50
100
200
400
500
300
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