MOTOROLA
SEMICONDUCTOR ADVANCE INFORMATION
DSP56362
Order this document by:
DSP56362/D
Rev 2.1, 11/00
1999, 2000, MOTOROLA, INC.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Advance Information
24-Bit Audio DIgital Signal Processor
Motorola designed the DSP56362 to support digital audio applications requiring digital audio
compression and decompression, sound field processing, acoustic equalization, and other digital
audio algorithms. The DSP56362 uses the high performance, single-clock-per-cycle DSP56300
core family of programmable CMOS digital signal processors (DSPs) combined with the audio
signal processing capability of the Motorola Symphony DSP family, as shown in Figure 1. This
design provides a two-fold performance increase over Motorola’s popular Symphony family of
DSPs while retaining code compatibility. Significant architectural enhancements include a barrel
shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56362
offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V.
Figure 1 DSP56362 Block Diagram
PLL
OnCE
Clock
Generator
Internal
Data
Bus
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODB/IRQB
MODC/IRQC
External
Data Bus
Switch
11
MODD/IRQD
DSP56300
12
16
24-Bit
24
18
DDB
DAB
Peripheral
Core
YM
_EB
XM_
E
B
PM
_
E
B
PIO
_
EB
Expansion Area
SHI
JTAG
6
5
RESET
MODA/IRQA
PINIT/NMI
EXTAL
Address
Control
Data
Triple
Timer
Host
Interface
ESAI
Address
Generation
Unit
Six Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24
× 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Mngmnt.
DRAM/SRAM
Bus
Interface
&
I - Cache
Control
External
Address
Bus
Switch
AA0456G
Memory
Expansion
Area
Program RAM/
Instruction
Cache
3072
× 24
Program ROM
30K
× 24
Bootstrap ROM
192
× 24
X Data
RAM
5632
× 24
ROM
6144
× 24
Y Data
RAM
5632
× 24
ROM
6144
× 24
CLKOUT
DAX
(SPDIF)
2