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| 型号： | SPC5517GAMMG66 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 1/54页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32B 1.5MB FLASH 208MAPBGA |
| 标准包装： | 90 |
| 系列： | MPC55xx Qorivva |
| 核心处理器： | e200z1 |
| 芯体尺寸： | 32-位 |
| 速度： | 66MHz |
| 连通性： | CAN，EBI/EMI，I²C，SCI，SPI |
| 外围设备： | DMA，POR，PWM，WDT |
| 输入/输出数： | 144 |
| 程序存储器容量： | 1.5MB（1.5M x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 80K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 数据转换器： | A/D 40x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 208-BGA |
| 包装： | 托盘 |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5510
Rev. 3, 3/2009
Freescale Semiconductor, Inc., 2007-2009. All rights reserved.
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
MPC5510
TBD
MAPBGA–225
15 mm x 15 mm
QFN12
##_mm_x_##mm
SOT-343R
##_mm_x_##mm
PKG-TBD
## mm x ## mm
MAPBGA–208
17 mm x 17 mm
LQFP–144
20 mm x 20 mm
LQFP–176
24 mm x 24 mm
MPC5510 Family Features
Single issue, 32-bit CPU core complex (e200z1)
– Compliant with the Power Architecture embedded
category
– Includes an instruction set enhancement allowing
variable length encoding (VLE) for code size footprint
reduction. With the optional encoding of mixed 16-bit
and 32-bit instructions, it is possible to achieve
significant code size footprint reduction.
Up to 1.5-Mbyte on-chip flash with flash control unit
(FCU)
Up to 80 Kbytes on-chip SRAM
Memory protection unit (MPU) with up to sixteen region
descriptors and 32-byte region granularity
Interrupt controller (INTC) capable of handling
selectable-priority interrupt sources
Frequency modulated Phase-locked loop (FMPLL)
Crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters
16-channel enhanced direct memory access controller
(eDMA)
Boot assist module (BAM) supports internal flash
programming via a serial link (CAN or SCI)
Timer supports input/output channels providing a range of
16-bit input capture, output compare, and pulse width
modulation functions (eMIOS200)
Up to 40-channel 12-bit analog-to-digital converter (ADC)
Up to four serial peripheral interface (DSPI) modules
Media Local Bus (MLB) emulation logic (works with two
DSPIs, the e200z0, the eDMA, and system RAM to create
a 3-pin or 5-pin 256Fs MLB protocol)
Up to eight serial communication interface (eSCI) modules
Up to six enhanced full CAN (FlexCAN) modules with
configurable buffers
One inter IC communication interface (I2C) module
Up to 144 configurable general purpose pins supporting
input and output operations and 3.0V through 5.5V supply
levels
Real-time counter (RTC_API) with clock source from
external 32-kHz crystal oscillator, internal 32-kHz or
16-MHz oscillator and supporting wake-up with selectable
1-second resolution and > 1-hour timeout, or 1-millisecond
resolution with maximum timeout of one second
Up to eight periodic interrupt timers (PIT) with 32-bit
counter resolution
Nexus development interface (NDI) per IEEE-ISTO
5001-2003 Class Two Plus standard
Device/board test support per Joint Test Action Group
(JTAG) of IEEE (IEEE 1149.1)
On-chip voltage regulator (VREG) for regulation of 5V
input to 1.5V and 3.3V internal supply levels
Optional e200z0, second Power Architecture based I/O
processor with VLE instruction set
Optional FlexRAY controller
Optional external bus interface (EBI) module
MPC5510 Microcontroller
Family Data Sheet
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