参数资料
型号: SPC560P44L3CEFB
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: MICROCONTROLLER, PQFP100
封装: ROHS COMPLIANT, LQFP-100
文件页数: 13/26页
文件大小: 509K
代理商: SPC560P44L3CEFB
SPC560P50x, SPC560P44x
Nexus 2+ features supported
Static debug
Watchpoint messaging
Ownership trace messaging
Program trace messaging
Real time read/write of any internally memory mapped resources through JTAG
pins
Overrun control, which selects whether to stall before Nexus overruns or keep
executing and allow overwrite of information
Watchpoint triggering, watchpoint triggers program tracing
Auxiliary Output Port
4 MDO (Message Data Out) pins
1 MCKO (Message Clock Out) pin
2 MSEO (Message Start/End Out) pins
–1 EVTO (Event Out) pin
Auxiliary Input Port
–1 EVTI (Event In) pin
3.3.29
IEEE 1149.1 JTAG controller
The JTAG controller (JTAGC) block provides the means to test chip functionality and
connectivity while remaining transparent to system logic when not in test mode. All data
input to and output from the JTAGC block is communicated in serial format. The JTAGC
block is compliant with the IEEE standard.
The JTAG controller provides the following features:
IEEE Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)
Selectable modes of operation include JTAGC/debug or normal system operation.
A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD
A 5-bit instruction register that supports the additional following public instructions:
ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE
Three test data registers: a bypass register, a boundary scan register, and a device
identification register. The size of the boundary scan register is parameterized to
support a variety of boundary scan chain lengths.
A TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry.
3.3.30
On-chip Voltage Regulator (VREG)
The on-chip voltage regulator module provides the following features:
Uses external NPN transistor
Regulates external 3.3V down to 1.2V for the core logic
Low voltage detection on the internal 1.2V and I/O voltage 3.3V
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