参数资料
型号: SPC5668EF1AVMG
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 116 MHz, MICROCONTROLLER, PBGA208
封装: 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MO-151AAF-1, MAPBGA-208
文件页数: 46/66页
文件大小: 599K
代理商: SPC5668EF1AVMG
MPC5668x Microcontroller Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
50
4.14.6
Deserial Serial Peripheral Interface (DSPI)
Table 29. DSPI Timing
Spec
Characteristic
Symbol
116 MHz1
1 116 MHz timing specified at CL = 50 pF with SRC = 0b11.
Unit
Min. Value
Max. Value
1
DSPI Cycle Time
Master (MTFE = 0)
Slave (MTFE = 0)
Master (MTFE = 1)
Slave (MTFE = 1)
tSCK
100
50
ns
2
PCS to SCK Delay2
2 The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].
tCSC
7—
ns
3
After SCK Delay3
3 The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].
tASC
14
ns
4
SCK Duty Cycle
tSDC
0.4
t
SCK
0.6
t
SCK
ns
5
Slave Access Time
(SS active to SOUT valid)
tA
25
ns
6
Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid)
tDIS
25
ns
7
PCSx to PCSS time
tPCSC
0—
ns
8PCSS to PCSx time
tPASC
0—
ns
9
Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)4
Master (MTFE = 1, CPHA = 1)
4 This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
tSUI
25
5
10
25
ns
10
Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)4
Master (MTFE = 1, CPHA = 1)
tHI
–4
7
12
–4
ns
11
Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO
8
28
15
8
ns
12
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
–7
2
1
–7
ns
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