
MC68336/376
REGISTER SUMMARY
MOTOROLA
USER’S MANUAL
Rev. 15 Oct 2000
D-58
D.7.6 FCSM Status/Interrupt/Control Register
COF — Counter Overflow Flag
This flag indicates whether or not a counter overflow has occurred. An overflow is de-
fined as the transition of the counter from $FFFF to $0000. If the IL[2:0] field is non-
zero, an interrupt request is generated when the COF bit is set.
0 = Counter overflow has not occurred
1 = Counter overflow has occurred
This flag bit is set only by hardware and cleared by software or system reset. To clear
the flag, first read the bit as a one, then write a zero to the bit.
IL[2:0] — Interrupt Level
When the FCSM generates an interrupt request, IL[2:0] determines which of the
interrupt request signals is asserted. When a request is acknowledged, the CTM4
compares IL[2:0] to a mask value supplied by the CPU32 to determine whether to
respond. IL[2:0] must have a value in the range of $0 (interrupts disabled) to $7
(highest priority).
IARB3 — Interrupt Arbitration Bit 3
This bit and the IARB[2:0] field in BIUMCR are concatenated to determine the interrupt
arbitration number for the submodule requesting interrupt service. Refer to
D.7.1 BIUDRV[A:B] — Drive Time Base Bus
This field controls the connection of the FCSM to time base buses A and B. Refer to
WARNING
Two time base buses should not be driven at the same time.
IN — Clock Input Pin Status
This read-only bit reflects the logic state of the clock input pin CTM2C. Writing to this
bit has no effect nor does reset.
FCSMSIC — FCSM Status/Interrupt/Control Register
$YFF460
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COF
IL[2:0]
IARB3
NOT
USED
DRVA DRVB
IN
NOT USED
CLK[2:0]
RESET:
U
0
U
0
Table D-39 Drive Time Base Bus Field
DRVA
DRVB
Bus Selected
0
Neither time base bus A nor bus B is driven
0
1
Time base bus B is driven
1
0
Time base bus A is driven
1
Both time base bus A and bus B are driven