参数资料
型号: SPT1019AIN
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: DAC
英文描述: PARALLEL, 8 BITS INPUT LOADING, 0.0055 us SETTLING TIME, 8-BIT DAC, PDIP24
封装: PLASTIC, DIP-24
文件页数: 6/12页
文件大小: 118K
代理商: SPT1019AIN
SPT
3
5/14/97
SPT1019
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
TEST LEVEL
I
II
III
IV
V
VI
ELECTRICAL SPECIFICATIONS
VCC =ground, VEE = -5.2 V ±0.3 V, TA =TMIN to TMAX, CC = 0 pF, ISet = 1.105 mA, unless otherwise specified.
TEST
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Reference Voltage
Measured to VCC
VI
1.3
-1.2
1.0
V
Input Capacitance,
V
3.0
pF
Data and Controls
Power Supply Sensitivity
VI
-120
20
+120
A/V
Supply Current
VI
155
220
mA
DYNAMIC CHARACTERISTICS (RL = 37.5 ohms, CL = 5 pF, TA = 25 °C, ISet = 1.105 mA)
Maximum Conversion Rate
B Grade
IV
165
MWPS
A Grade
IV
275
MWPS
Rise Time
10% to 90% G.S.
IV
1.6
ns
TA = TMIN to TMAX
IV
2.0
ns
Rise Time
10% to 90% G.S.
V
1.0
ns
RL = 25 ohms
Current Settling Time, Clocked Mode
To 0.2% G.S.
V
7.0
ns
Current Settling Time, Clocked Mode
To 0.8% G.S.
V
5.5
ns
Current Settling Time, Clocked Mode
To 0.2% G.S.
V
4.5
ns
tSI
RL = 25
Clock to Output Delay, Clocked Mode
IV
2.2
4.0
ns
tDSC
TA = TMIN to TMAX
IV
4.5
ns
Data to Output Delay,
IV
3.2
6.0
ns
Transparent Mode tDST
IV
6.0
ns
Convert Pulse Width, ( LOW or HIGH)
B Grade
IV
3.0
ns
tPWL, tPWH
A Grade
IV
1.8
ns
Glitch Energy
Area = 1/2 VT
V
4
pV-s
Reference Bandwidth, -3 dB
V
1.0
MHz
Setup Time, Data and Controls
IV
1.0
ns
tS
TA = TMIN to TMAX
IV
1.0
ns
Hold Time, Data and Controls
IV
0.5
ns
tH
TA = TMIN to TMAX
IV
0.5
ns
Slew Rate
20% to 80% G.S.
IV
390
V/
S
TA = TMIN to TMAX
IV
325
V/
S
Clock Feedthrough
IV
-48
dB
TA = TMIN to TMAX
IV
-48
dB
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