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参数资料
| 型号： | SPT5240SIT |
| 厂商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分类： | DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.104 us SETTLING TIME, 10-BIT DAC, PQFP32 |
| 封装： | TQFP-32 |
| 文件页数： | 6/8页 |
| 文件大小： | 67K |
| 代理商： | SPT5240SIT |
SPT
6
12/15/01
SPT5240
Figure 2 – Typical Interface Circuit
TYPICAL INTERFACE CIRCUIT
The SPT5240 requires few external components to
achieve the stated performance. Figure 2 shows the typi-
cal interface requirements when used in normal circuit
operation. The following sections provide descriptions of
the major functions and outline performance criteria to
consider for achieving optimal performance.
DIGITAL INPUTS
The SPT5240 has a 10-bit-wide parallel data input de-
signed to work at +3.3 V CMOS levels. Fast edges and low
transients provide for improved performance.
CLOCK INPUT
The SPT5240 is driven by a single-ended clock circuit. In
order to achieve best performance at the highest through-
put, a clock generation circuit should provide fast edges
and low jitter.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection cir-
cuit. This circuit provides robust ESD protection in excess
of 3,000 volts, in human body model, without sacrificing
speed.
POWER SUPPLIES AND GROUNDING
The SPT5240 may be operated in the range of 2.8 to 3.6
volts. Normal operation is recommended to be separate
analog and digital supplies operating at +3.3 volts. All
power supply pins should be bypassed as close to the
package as possible with the smallest capacitor closest to
the device. Analog and digital ground planes should be
connected together with a ferrite bead as shown in figure 2
and as close to the DAC as possible.
SLEEP MODE
To conserve power, the SPT5240 incorporates a power-
down function. This function is controlled by the signal on
pin PWD. When PWD is set high, the SPT5240 enters the
sleep mode. The analog outputs are both set to zero cur-
rent output, resulting in less than 500 nA current draw from
the analog supply. For minimum power dissipation, data
and clock inputs should be removed.
FB
50
.01 F
.1 F
10 F
.01 F
.1 F
10 F
+D3.3 V
+A3.3 V
RSET
Clock In
Reference
Voltage
Out
Sleep
Mode
Select
IOUT
Adjust
CLK ISET VRNL
PWD
DV
DD
DGND
AGND
AV
DD
IOP
ION
D0D9
In
10-Bit
Data Bus
SPT5240
Notes:
1. FB = Ferrite bead across analog and digital
ground planes. Place as close to DAC as feasible.
2. VRNL is a no-load output. Use for monitoring
purposes only.
3. Minimum resistance (RSET) from ISET to ground
results in maximum current output.
4. PWD pin has an internal pull-down resistor. Set
pin high to initiate sleep mode.
5. Outputs (IOP and ION) require minimum 5 W
load.
VOP
VON
+
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SPT5240SIT_Q | 功能描述:数模转换器- DAC 10BIT 400MWPS 3V DaC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| SPT5303 | 制造商:SSDI 制造商全称:Solid States Devices, Inc 功能描述:200 WATT NPN SILICON POWER TRANSISTOR |
| SPT5310 | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12-BIT, 250 MWPS ECL D/A CONVERTER |
| SPT5310SIN | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12-BIT, 250 MWPS ECL D/A CONVERTER |
| SPT5310SIP | 制造商:CADEKA 制造商全称:CADEKA 功能描述:12-BIT, 250 MWPS ECL D/A CONVERTER |
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