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参数资料
| 型号： | SPT5320SIS |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.025 us SETTLING TIME, 12-BIT DAC, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 2/4页 |
| 文件大小： | 36K |
| 代理商： | SPT5320SIS |
SPT
2
8/24/00
SPT5320
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Note 1: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in typical
applications.
Supply Voltages
AVDD .................................................... –0.3 V to +6.5 V
DVDD ................................................... –0.3 V to +6.5 V
AGND, DGND, RGND ......................... –0.3 V to +0.3 V
AGND – DGND .............................................. ±300 mV
Input Voltages
Digital Inputs ............................. –0.3 V to DVDD + 0.3 V
VREF, RSET ................................ –0.3 V to AVDD + 0.3 V
COMP ...................................... –0.3 V to AVDD + 0.3 V
Output
IOUTA, IOUTB Current ............................................ 15 mA
IOUTA, IOUTB Voltage ...................... –1.0 to AVDD + 0.3 V
Temperature
Operating Temperature ........................... –40 to +85 °C
Junction Temperature ...................................... +175 °C
Lead Temperature, (soldering 10 seconds) ...... +300 °C
Storage Temperature ............................ –65 to +150 °C
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, unless otherwise specified.
TEST
SPT5320
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
DC Performance
Resolution
12
Bits
Differential Linearity
25 °C
±0.5
LSB
Differential Linearity
Full Temp.
±1.0
LSB
Integral Linearity
25 °C
±1.0
LSB
Integral Linearity
Full Temp.
±2.0
LSB
Offset Error
±0.025
% FS
Gain Error (without internal reference)
±2
±10
% FS
Gain Error (with internal reference)
±1
±10
% FS
Full-Scale Output Current
20.48
mA
Output Compliance Voltage
–1.0
+1.25
V
Equivalent Output Resistance
>100
k
Gain Error Tempco
tbd
PPM/°C
Zero-Scale Offset Error
±0.025
% FS
Output Capacitance
5pF
Offset Drift
tbd
ppm FS/°C
Gain Drift (without internal reference)
±50
ppm FS/°C
Gain Drift (with internal reference)
±100
ppm FS/°C
Dynamic Performance
Maximum Output Update Rate
160
MWPS
Output Settling Time (to 0.1%)
25
35
ns
Output Propagation Delay
tbd
ns
Glitch Impulse
5pV-s
Output Rise Time (10% to 90%)
tbd
ns
Output Fall Time (10% to 90%)
tbd
ns
Output Noise (IOUTFS = 10 mA)
25
50
pA/
√Hz
Spurious Free Dynamic Range to Nyquist
CLK = 50 MHz; OUT = 20 MHz
67
dBc
CLK = 100 MHz; OUT = 20 MHz
67
dBc
CLK = 160 MHz; OUT = 20 MHz
63
dBc
Spurious Free Dynamic Range within a Window
CLK = 50 MHz; OUT = 5 MHz; 2 MHz Span
86
dBc
CLK = 100 MHz; OUT = 5 MHz; 4 MHz Span
86
dBc
Multitone Power Ratio (8 Tones at 110 kHz Spacing)
CLK = 20 MHz; OUT = 2.00 to 2.99 MHz
75
dBc
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