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参数资料
| 型号： | SPT5450SIS |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.025 us SETTLING TIME, 14-BIT DAC, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 3/4页 |
| 文件大小： | 36K |
| 代理商： | SPT5450SIS |
SPT
3
8/24/00
SPT5450
TEST LEVEL CODES
All electrical characteristics are subject
to the following conditions:
All parameters having min/max specifi-
cations are guaranteed. The Test Level
column indicates the specific device
testing actually performed during pro-
duction and Quality Assurance inspec-
tion. Any blank section in the data
column indicates that the specification
is not tested at the specified condition.
TEST LEVEL
TEST PROCEDURE
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design and characteriza-
tion data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed over
specified temperature range.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=+5.0 V, unless otherwise specified.
TEST
SPT5450
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Power Supply Requirements
Analog Supply Voltage AVDD
4.5
5.5
V
Digital Supply Voltage DVDD
2.7
5.5
V
Analog Supply Current
tbd
mA
Digital Supply Current
tbd
mA
Supply Current Sleep Mode
tbd
5
mA
Power Dissipation
At +3 V Supplies and 10 mA Current Output
100
mW
At +5 V Supplies and 10 mA Current Output
300
mW
Power Supply Rejection Ratio (AVDD)
±0.02
±0.2
%FS/V
Power Supply Rejection Ratio (DVDD)
±0.002
±0.025
%FS/V
Reference
Reference Voltage
1.20
V
Reference Output Current
tbd
Reference Input Compliance Range
0.1
1.25
V
Small Signal Bandwidth
tbd
MHz
Reference Voltage Drift
±50
ppm/°C
Digital Inputs
Logic “1” Voltage (DVDD = +3 V)
2.1
V
Logic “0” Voltage (DVDD = +3 V)
0.9
V
Logic “1” Voltage (DVDD = +5 V)
3.5
V
Logic “0” Voltage (DVDD = +5 V)
1.3
V
Logic “1” Current
–10
+10
A
Logic “0” Current
–10
+10
A
Input Capacitance
35
pF
Input Setup Time – tS
2<1
ns
Input Hold Time – tH
2<1
ns
Latch Pulse Width – tLPW
tbd
ns
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