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参数资料
| 型号： | SPT674CCJ |
| 厂商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分类： | ADC |
| 英文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP28 |
| 封装： | SIDE BRAZED, CERAMIC, DIP-28 |
| 文件页数： | 7/12页 |
| 文件大小： | 103K |
| 代理商： | SPT674CCJ |
SPT
4
8/1/00
SPT674
ELECTRICAL SPECIFICATIONS
TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 117 kHz, fIN = 10 kHz, unless otherwise specified.
TEST
SPT674C
SPT674B
PARAMETER
CONDITIONS
LEVEL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS4
Convert Mode Timing
tDSC STS Delay from CE
VI
60
200
60
200
ns
tHEC CE Pulse Width
VI
50
30
50
30
ns
tSSC CS to CE Setup
VI
50
20
50
20
ns
tHSC CS Low during CE High
VI
50
20
50
20
ns
tSRC R/C to CE Setup
VI
50
0
50
0
ns
tHRC R/C Low During CE High
VI
50
20
50
20
ns
tSAC Ao to CE Setup
VI
0
ns
tHAC Ao Valid During CE High
VI
50
20
50
20
ns
tC Conversion Time5
12-Bit Cycle
VI
9
13
15
9
13
15
s
8-Bit Cycle
VI
6
8
10
6
8
10
s
Read Mode Timing
tDD Access Time from CE
VI
75
150
75
150
ns
tHD Data Valid After CE Low
VI
25
35
25
35
ns
tHL Output Float Delay
VI
100
150
100
150
ns
tSSR CS to CE Setup
VI
50
0
50
0
ns
tSRR R/C to CE Setup
VI
0
ns
tSAR Ao to CE Setup
VI
50
25
50
25
ns
tHSR CS Valid After CE Low
VI
0
ns
tHRR R/C High After CE Low
VI
0
ns
tHS STS Delay After Data Valid
VI
100
300
600
100
300
600
ns
tHAR Ao Valid after CE Low
VI
50
ns
Note 4: Time is measured from 50% level of digital transitions.
Note 5: Includes acquisition time.
tHEC
t
SSC
t SRC
t HSC
t HRC
t
HAC
t SAC
t DSC
High Impedance
tC
DB11-DB0
STS
Ao
R/C
CE
CS
Figure 1 - Convert Mode Timing Diagram
Figure 2 - Read Mode Timing Diagram
t SSR
Ao
CE
CS
t HSR
t HRR
t SRR
t SAR
t HAR
STS
DATA
VALID
t HL
HIGH
IMPEDANCE
DB11-DB0
R/C
t HS
t HD
t DD
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