参数资料
型号: SPT7730SCU
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: ADC
英文描述: 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, UUC8
封装: DIE
文件页数: 5/8页
文件大小: 82K
代理商: SPT7730SCU
5
12/19/97
SPT7730
Figure 1 - Analog Input Full-Scale Range
VREF+
6% of [(VREF+) - (VREF-)]
VREF-
+FS
-FS
Full-Scale
Range
4% of [(VREF+) - (VREF-)]
The drive requirements for the analog input are minimal
when compared to most other converters due to the
SPT7730’s extremely low input capacitance of only 5 pF and
very high input resistance of greater than 5 M
.
If the input buffer amplifier supply voltages are greater than
VDD + 0.7 V or less than Ground - 0.7 V, the analog input
should be protected through a series resistor and a diode
clamping circuit as shown in figure 2.
Figure 2 - Recommended Input Protection Circuit
47
D1
D2
ADC
Buffer
AVDD
+V
-V
D1 = D2 = Hewlett Packard HP5712 or equivalent
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 3. This circuit provides ESD robustness to
>3.0 kV and prevents latch-up under severe discharge
conditions without degrading analog transition times.
Figure 3 - On-Chip Protection Circuit
VDD
Analog
Pad
120
120
MODES OF OPERATION
The SPT7730 has three modes of operation.The mode of
operation is based strictly on how the SC is used.
SINGLE SHOT MODE
When SC goes low, conversion starts on the next rising edge
of the clock (defined as the first conversion clock). The MSB
of data is valid 8 ns after the falling edge of the fourth
conversion clock. (See figure 8.)
The conversion is complete after 12 clock cycles. At the
falling edge of the twelfth clock cycle, if SC is high (not
selected), the data output goes to a high impedance state,
and no more conversions will take place until the next SC low
event. (See the single shot mode timing diagram in figure 4.)
SYNCHRONIZED MODE
When SC goes low, conversion will start on the next rising
edge of the clock (defined as the first conversion clock). The
MSB is valid 8 ns after the falling edge of the fourth conver-
sion clock.
The first conversion is complete after 12 clock cycles. At
any time after the falling edge of the twelfth clock cycle, SC
may go low again to initiate the next conversion. When the
SC goes low, the conversion starts on the rising edge of the
next clock. (See the synchronized mode timing diagram
in figure 5.)
The data output will go to a high impedance state until the
next conversion is initiated.
FREE RUN MODE
When SC goes low, conversion starts on the next rising edge
of the clock (defined as the first conversion clock). The MSB
data is valid 8 ns after the falling edge of the fourth conver-
sion clock.
As long as SC is held low, the device operates in the free run
mode. New conversions start after every twelfth cycle with
valid data available 8 ns after the falling edge of the fourth
clock within each new conversion cycle.
The data output remains low between conversion cycles.
(See the free run mode timing diagram in figure 6.)
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SPT7734 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:8-BIT, 40 MSPS,175 mW A/D CONVERTER
SPT7734SCS 功能描述:视频模拟/数字化转换器集成电路 8BIT 40 MSPS SaR aDC RoHS:否 制造商:Texas Instruments 输入信号类型:Differential 转换器数量:1 ADC 输入端数量:4 转换速率:3 Gbps 分辨率:8 bit 结构: 输入电压:3.3 V 接口类型:SPI 信噪比: 电压参考: 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TCSP-48 封装:Reel
SPT7734SCS_Q 功能描述:模数转换器 - ADC 8BIT 40 MSPS SaR aDC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32
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SPT7734SCT_Q 功能描述:模数转换器 - ADC 8BIT 40 MSPS SaR aDC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32