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参数资料
| 型号： | SPT7860SCS |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | SOIC-28 |
| 文件页数： | 12/12页 |
| 文件大小： | 193K |
| 代理商： | SPT7860SCS |
9
5/25/01
SPT7860
Typically, the top side voltage drop for VRHF to VRHS will
equal:
VRHF – VRHS = 2.25 % of (VRHF – VRLF) (typical),
and the bottom side voltage drop for VRLS to VRLF will
equal:
VRLS – VRLF = 1.9 % of (VRHF – VRLF) (typical).
Figure 4 shows an example of expected voltage drops for
a specific case. VREF of 4.0 V is applied to VRHF, and VRLF
is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V),
and a 75 mV increase is seen at VRLS (= 0.075 V).
ANALOG INPUT
VIN is the analog input. The input voltage range is from
VRLS to VRHS (typically 4.0 V) and will scale proportionally
with respect to the voltage reference. (See voltage refer-
ence section.)
The drive requirements for the analog inputs are very
minimal when compared to most other converters due to
the SPT7860’s extremely low input capacitance of only
5 pF and very high input resistance of 50 k
.
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 5.
Upon powerup, the SPT7860 begins its calibration algo-
rithm. In order to achieve the calibration accuracy re-
quired, the offset and gain adjustment step size is a frac-
tion of a 10-bit LSB. Since the calibration algorithm is an
oversampling process, a minimum of 10,000 clock cycles
are required. This results in a minimum calibration time
upon powerup of 250 sec (for a 40 MHz clock). Once
calibrated, the SPT7860 remains calibrated over time and
temperature.
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7860 to remain in calibration.
INPUT PROTECTION
All I/O pads are protected with an on-chip protection
circuit shown in figure 6. This circuit provides ESD robust-
ness to 3.5 kV and prevents latch-up under severe dis-
charge conditions without degrading analog transition
times.
Figure 5 – Recommended Input Protection Circuit
47 W
D1
D2
ADC
Buffer
AVDD
+V
V
D1 = D2 = Hewlett-Packard HP5712 or equivalent
Figure 6 – On-Chip Protection Circuit
VDD
Analog
Pad
120 W
CALIBRATION
The SPT7860 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and off-
set errors are continually adjusted to 10-bit accuracy
during device operation. This process is completely trans-
parent to the user.
POWER SUPPLY SEQUENCING CONSIDERATIONS
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decou-
pling networks with large time constants that could delay
VDD power to the device.
CLOCK INPUT
The SPT7860 is driven from a single-ended TTL-input
clock. Because the pipelined architecture operates on the
rising edge of the clock input, the device can operate over
a wide range of input clock duty cycles without degrading
the dynamic performance.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SPT7860SCSX | 功能描述:直流/直流开关转换器 RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| SPT7860SCT | 功能描述:视频模拟/数字化转换器集成电路 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 输入信号类型:Differential 转换器数量:1 ADC 输入端数量:4 转换速率:3 Gbps 分辨率:8 bit 结构: 输入电压:3.3 V 接口类型:SPI 信噪比: 电压参考: 电源电压-最大:3.45 V 电源电压-最小:3.15 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:TCSP-48 封装:Reel |
| SPT7860SCT_Q | 功能描述:模数转换器 - ADC 10BIT 40MSPS SaR aDC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| SPT7860SCTX | 功能描述:直流/直流开关转换器 RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| SPT7861 | 制造商:CADEKA 制造商全称:CADEKA 功能描述:10-BIT, 40 MSPS, 160 mW A/D CONVERTER |
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