参数资料
型号: SPT7861SCU
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: ADC
英文描述: 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, UUC28
封装: DIE-28
文件页数: 1/8页
文件大小: 91K
代理商: SPT7861SCU
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300
FAX: (719) 528-2370
SPT
SIGNAL PROCESSING TECHNOLOGIES
GENERAL DESCRIPTION
The SPT7861 is a 10-bit monolithic, low cost, ultralow-power
analog-to-digital converter capable of minimum word rates of
40 MSPS. This is a pin-compatible improved version of the
SPT7860. The on-chip track-and-hold function assures ex-
cellent dynamic performance without the need for external
components. The input drive requirements are minimized
due to the SPT7861's low input capacitance of only 5 pF.
Power dissipation is extremely low at only 160 mW typical at
40 MSPS with a power supply of +5.0 V. The digital outputs
are +3 V or +5 V, and are user selectable. The SPT7861 is
SPT7861
10-BIT, 40 MSPS,160 mW A/D CONVERTER
FEATURES
Monolithic 40 MSPS Converter
160 mW Power Dissipation
On-Chip Track-and-Hold
Single +5 V Power Supply
TTL/CMOS Outputs
5 pF Input Capacitance
Low Cost
Tri-State Output Buffers
High ESD Protection: 3,500 V Minimum
Selectable +3 V or +5 V I/O
APPLICATIONS
All High-Speed Applications In Which
Low Power Dissipation is Required
Video Imaging
Medical Imaging
Radar Receivers
IR Imaging
Digital Communications
pin compatible with the entire family of SPT 10-bit, CMOS
converters (SPT7835/40/50/55/60/61) which simplifies up-
grades. The SPT7861 has incorporated proprietary circuit
design and CMOS processing technologies to achieve its
advanced performance. Inputs and outputs are TTL/CMOS
compatible to interface with TTL/CMOS logic systems. Out-
put data format is straight binary.
The SPT7861 is available in 28-lead SOIC and 32-lead small
(7 mm square) TQFP packages over the commercial tem-
perature range. For availability of extended temperatureranges,
consult the factory.
BLOCK DIAGRAM
..
.
11-Bit
SAR
DAC
ADC Section 1
T/H
11
11-Bit
SAR
DAC
ADC Section 16
Auto-
Zero
CMP
Auto-
Zero
CMP
T/H
11
VREF
1:16
Mux
.
11
11-Bit
16:1
Mux/
Error
Correction
Timing
and
Control
P1
P2
P15
P16
ADC Section 2
ADC Section 15
.
Reference Ladder
Ref
In
Enable
CLK In
Data
Valid
AIN
.
D10 Overrange
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
D (LSB)
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