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参数资料
| 型号： | SPT7883SIR |
| 厂商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分类： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | SSOP-28 |
| 文件页数： | 6/8页 |
| 文件大小： | 78K |
| 代理商： | SPT7883SIR |
SPT
6
11/21/01
SPT7883
DIGITAL OUTPUTS
When the output enable is set high, then the digital output
data appears in offset binary code at CMOS 2.5 V logic
levels. Full-scale negative input results in output code
000…0. Full-scale positive input results in output code
111…1. Output data is available 6 clock cycles after the
data is sampled. The analog input is sampled one aperture
delay (tAP) after the high-to-low clock transition. Output
data should be sampled as shown in the timing diagram
above.
When the output enable is set low, then the digital output
data goes into a high Z-mode.
Figure 2 – Timing Diagram
PCB LAYOUT AND DECOUPLING
A well designed PCB is necessary to get good spectral
purity from any high-performance ADC. A multilayer PCB
with a solid ground plane is recommended for optimum
performance. If the system has a split analog and digital
ground plane, it is recommended that all ground pins on
the ADC be connected to the analog ground plane
(AGND). All digital interface circuits are connected to the
digital ground (DGND). AGND and DGND planes must be
connected through a ferrite bead placed as close to the
ADC as possible. Refer to the typical interface circuit
diagram (figure 1) or AN7883 application note for recom-
mended decoupling and PCB layout.
N1
N
N+1
N+2
N+3
Data
N1
Data
N
Data
N+1
Data
N+2
Data
Clock
tAP
tH
tD
AIN
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