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参数资料
| 型号： | SPT9689BIP |
| 厂商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分类： | 运动控制电子 |
| 英文描述： | DUAL ULTRAFAST VOLTAGE COMPARATOR |
| 中文描述： | DUAL COMPARATOR, 30000 uV OFFSET-MAX, PQCC20 |
| 封装： | PLASTIC, LCC-20 |
| 文件页数： | 4/8页 |
| 文件大小： | 75K |
| 代理商： | SPT9689BIP |
4
2/20/01
SPT9689
SWITCHING TERMS (Refer to figure 1)
t
pdH
INPUT TO OUTPUT HIGH DELAY
–
the propaga-
tion delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output LOW to HIGH transition
t
pdL
INPUT TO OUTPUT LOW DELAY
–
the propagation
delay measured from the time the input signal
crosses the reference (± the input offset voltage) to
the 50% point of an output HIGH to LOW transition
t
pLOH
LATCH ENABLE TO OUTPUT HIGH DELAY
–
the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output LOW to HIGH transition
V
OD
VOLTAGE OVERDRIVE
–
the difference between
the differential input and reference input voltages
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY
–
the
propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to
the 50% point of an output HIGH to LOW transition
t
H
MINIMUM HOLD TIME
–
the minimum time after the
negative transition of the Latch Enable signal that
the input signal must remain unchanged in order to
be acquired and held at the outputs
t
pL
MINIMUM LATCH ENABLE PULSE WIDTH
–
the
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change
t
S
MINIMUM SET-UP TIME
–
the minimum time before
the negative transition of the Latch Enable signal
that an input signal change must be present in order
to be acquired and held at the outputs
GENERAL INFORMATION
The SPT9689 is an ultrahigh-speed dual voltage com-
parator. It offers tight absolute characteristics. The device
has differential analog inputs and complementary logic
outputs compatible with ECL systems. The output stage is
adequate for driving terminated 50 ohm transmission
lines.
The SPT9689 has a complementary latch enable control
for each comparator. Both should be driven by standard
ECL logic levels.
The negative common mode voltage is
–
2.5 V. The posi-
tive common mode voltage is +4.0 V.
The dual comparators share the same V
CC
and V
EE
con-
nections but have separate grounds for each comparator
to achieve high crosstalk rejection.
3
4
Figure 2 – Internal Function Diagram
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相关代理商/技术参数 |
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| SPT9691 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:WIDE INPUT VOLTAGE, JFET COMPARATOR |
| SPT9691SCC | 功能描述:校验器 IC JFET COMPARATR 2.5ns <100pA -4 - +8V RoHS:否 制造商:STMicroelectronics 产品: 比较器类型: 通道数量: 输出类型:Push-Pull 电源电压-最大:5.5 V 电源电压-最小:1.1 V 补偿电压（最大值）:6 mV 电源电流（最大值）:1350 nA 响应时间: 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:SC-70-5 封装:Reel |
| SPT9691SCN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:WIDE INPUT VOLTAGE, JFET COMPARATOR |
| SPT9691SCP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:WIDE INPUT VOLTAGE, JFET COMPARATOR |
| SPT9691SCU | 制造商:未知厂家 制造商全称:未知厂家 功能描述:WIDE INPUT VOLTAGE, JFET COMPARATOR |
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