- 您现在的位置：买卖IC网 > PDF目录382545 > SPT9713AIP (SIGNAL PROCESSING TECHNOLOGIES) 12-BIT, 100 MWPS TTL D/A CONVERTER PDF资料下载
参数资料
| 型号： | SPT9713AIP |
| 厂商： | SIGNAL PROCESSING TECHNOLOGIES |
| 元件分类： | DAC |
| 英文描述： | 12-BIT, 100 MWPS TTL D/A CONVERTER |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.013 us SETTLING TIME, 12-BIT DAC, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 4/7页 |
| 文件大小： | 48K |
| 代理商： | SPT9713AIP |
4
2/15/01
SPT9713
THEORY OF OPERATION
The SPT9713 uses a segmented architecture incorporat-
ing most significant bit (MSB) decoding. The four MSBs
(D1–D4) are decoded to thermometer code lines to drive
15 discrete current sinks. For the eight least significant
bits (LSBs), D5 and D6 are binary weighted and D7–D12
are applied to the R-2R network. The 12-bit decoded data
is input to internal master/slave latches. The latched data
is input to the switching network and is presented on the
output pins as complementary current outputs.
TYPICAL INTERFACE CIRCUIT
The SPT9713 requires few external components to
achieve the stated operation and performance. Figure 2
shows the typical interface requirements when using the
SPT9713 in normal circuit operation. The following sec-
tions provide descriptions of the pin functions and outline
critical performance criteria to consider for achieving opti-
mal device performance.
POWER SUPPLIES AND GROUNDING
The SPT9713 requires the use of +5 V and –5.2 V sup-
plies. All supplies should be treated as analog supply
sources. This means the ground returns of the device
should be connected to the analog ground plane. All sup-
ply pins should be bypassed with .01 μF and 10 μF
decoupling capacitors as close to the device as possible.
The two grounds available on the SPT9713 are DGND
and AGND. These grounds are not tied together internal to
the device. The use of ground planes is recommended to
achieve the best performance of the SPT9713. All ground,
reference and analog output pins should be tied directly to
the DAC ground plane. The DAC and system ground
planes should be separate from each other and only con-
nected at a single point through a ferrite bead to reduce
ground noise pickup.
DIGITAL INPUTS AND TIMING
The SPT9713 uses TTL logic drivers for each data input
D1–D12 and Latch Enable. It also employs master/slave
latches to simplify digital interface timing requirements
and reduce glitch energy by synchronizing the current
switches. This is an improvement over the AD9713, which
typically requires external latches for digital input synchro-
nization.
Referring to figure 1, data is latched into the DAC on the
rising edge of the latch enable clock with the associated
setup and hold times. The output transition occurs after a
typical 2 ns propagation delay and settles to within ±1 LSB
in typically 13 ns. Because of the SPT9713’s rising-edge
triggering, no timing changes are required when replacing
an AD9713 operating in the transparent mode.
VOLTAGE REFERENCE
When using the internal reference, Ref Out should be con-
nected to Control Amp In and decoupled with a 0.1 μF
capacitor. Control Amp Out should be connected to Ref In
and decoupled to the analog supply. (See figure 2.)
Full-scale output current is determined by Control Amp In
and R
Set
using the following formula:
I
Out
(FS) = (Control Amp In / R
Set
) x 128
(Current Out is a constant 128 factor of the
reference current)
The internal reference is typically –1.20 V with a tolerance
of ±0.05 V and a typical drift of 50 ppm/°C. If greater accu-
racy or temperature stability is required, an external refer-
ence can be utilized.
OUTPUTS
The output of the SPT9713 is comprised of complemen-
tary current sinks, I
Out
and I
Out
. The output current levels
at either I
Out
or I
Out
are based upon the digital input code.
The sum of the two is always equal to the full-scale output
current minus one LSB.
By terminating the output current through a resistive load
to ground, an associated voltage develops. The effective
resistive load (R
Eff
) is the output resistance of the device
(R
Out
) in parallel with the resistive load (R
L
). The voltage
which develops can be determined using the following
formulas:
Control Amp Out = –1.2 V, and R
Set
= 7.5 k
I
Out
(FS) = (–1.2 V / 7.5 k
) x 128 = –20.48 mA
R
L
= 51
R
Out
= 1.0 k
R
Eff
= 51
|| 1.0 k
= 48.52
V
Out
= R
Eff
x I
Out
(FS) = 48.52
x –20.48 mA
= –0.994 V
The resistive load of the SPT9713 can be modified to in-
corporate a wide variety of signal levels. However, optimal
device performance is achieved when the outputs are
equivalently loaded.
相关PDF资料 |
PDF描述 |
|---|---|
| SR1110 | TECHNICAL SPECIFICATIONS OF SCHOTTKY BARRIER RECTIFIER |
| SR203 | SCHOTTKY BARRIER RECTIFIERS(2.0A,20-60V) |
| SR203 | 2 Amp Schottky Barrier Rectifier 20 - 60 Volts |
| SR204 | Datamate Trio-Tek DIL Female Housing, with Reverse Fix jackscrews, 5+5-way |
| SR206 | 2 Amp Schottky Barrier Rectifier 20 - 60 Volts |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SPT9713BIP | 功能描述:数模转换器- DAC D/A CONVERTER 12-BIT 100MWPS 640mW RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| SPTA 1.5/ 4-5.08 | 制造商:Vishay BCcomponents 功能描述: |
| SPTA 1/ 2-5.0 | 制造商:Vishay BCcomponents 功能描述: |
| SPTA 1/ 4-5.0 | 制造商:Phoenix Contact 功能描述:Conn PC Terminal Block F 4 POS 5mm Solder Thru-Hole 9A |
| SPTA 1/10-3.5 | 制造商:Phoenix Contact 功能描述:TERM BLK PCB SPRING 3.5MM 10WAY 制造商:Phoenix Contact 功能描述:TERM BLOCK, PCB, SPRING, 3.5MM, 10P 制造商:Phoenix Contact 功能描述:TERM BLOCK, PCB, SPRING, 3.5MM, 10P; Connector Type:Terminal Block, PCB; Connector Mounting:PCB; Pitch Spacing:3.5mm; No. of Contacts:10; Wire Size AWG Min:24AWG; Wire Size AWG Max:16AWG; Contact Plating:Tin; Contact Material:Copper;;RoHS Compliant: Yes |
发布紧急采购，3分钟左右您将得到回复。