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| 型号： | SR12.TCT |
| 厂商： | Semtech |
| 文件页数： | 5/8页 |
| 文件大小： | 0K |
| 描述： | IC TVS ARRAY 2-LINE 12V SOT-143 |
| 标准包装： | 1 |
| 系列： | RailClamp® |
| 电压 - 反向隔离（标准值）： | 12V |
| 电压 - 击穿： | 13.3V |
| 功率（瓦特）： | 500W |
| 电极标记： | 2 通道阵列 - 单向 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-253-4，TO-253AA |
| 供应商设备封装： | SOT-143 |
| 包装： | 标准包装 |
| 产品目录页面： | 1357 (CN2011-ZH PDF) |
| 其它名称： | SR12DKR |
SR12
PROTECTION PRODUCTS
Applications Information (continued)
For negative events, the bottom diode will be biased
when the voltage exceeds the V F of the diode. At first
approximation, the clamping voltage due to the charac-
teristics of the protection diodes is given by:
V = V CC + V F (for C
PIN Descriptions positive duration pulses)
V C = -V F (for negative duration pulses)
However, for fast rise time transient events, the
effects of parasitic inductance must also be consid-
ered as shown in Figure 2. Therefore, the actual
clamping voltage seen by the protected circuit will be:
V C = V CC + V F + L P di ESD /dt (for positive duration pulses)
V C = -V F - L G di ESD /dt (for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 1000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = L P di ESD /dt = 1X10 -9 (30 / 1X10 -9 ) = 30V
Example:
Consider a V CC = 5V, a typical V F of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
V C = 5V + 30V + (10nH X 30V/nH) = 335V
This does not take into account that the ESD current is
directed into the supply rail, potentially damaging any
components that are attached to that rail. Also note
that it is not uncommon for the V F of discrete diodes to
exceed the damage threshold of the protected IC. This
is due to the relatively small junction area of typical
discrete components. It is also possible that the
power dissipation capability of the discrete diode will
be exceeded, thus destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression. The RailClamp’s integrated TVS diode
helps to mitigate the effects of parasitic inductance in
Figure 1 - “Rail-T o-Rail ” Pro t ection Topology
(First Approximation)
Figure 2 - The Effects of Parasitic Inductance
When Using Discrete Components to Implement
Rail-T o-Rail Pro t ection
Figure 3 - Rail-T o-Rail Pro t ection Using
RailClamp T V S Arrays
? 2005 Semtech Corp.
5
www.semtech.com
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