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参数资料
| 型号： | SR2.8TG |
| 厂商： | Semtech Corporation |
| 英文描述： | RailClamp Low Capacitance TVS Diode Array |
| 中文描述： | RailClamp低电容二极管二极管阵列 |
| 文件页数： | 5/8页 |
| 文件大小： | 103K |
| 代理商： | SR2.8TG |
5
2000 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
Applications Information
(continued)
the TVS clamping voltage and the voltage due to the
parasitic inductance (V
= V
+ L di/dt) .
Parasitic
inductance in the protection path can result in signifi-
cant voltage overshoot, reducing the effectiveness of
the suppression circuit.
An ESD induced transient for
30A pulse (per IEC 61000-4-2 Level 4), 1nH of series
inductance will increase the effective clamping voltage
by 30V
(V = 1x10
-9
(30/1x10
-9
)). For maximum effectiveness,
the following board layout guidelines are recom-
mended:
SR2.8
PIN Descriptions
I
PP
I
SB
I
PT
I
R
V
RWM
V
V
PT
V
C
V
BRR
I
BRR
SB
Figure 1 - EPD TVS IV Characteristic Curve
"
Minimize the path length between the SR2.8 and
the protected line.
Place the SR2.8 near the RJ45 connector to
restrict transient coupling in nearby traces.
Minimize the path length (inductance) between the
RJ45 connector and the SR2.8.
"
"
EPD TVS Characteristics
The internal TVS of the SR2.8 is constructed using
Semtech’s proprietary EPD technology. The structure
of the EPD TVS is vastly different from the traditional
pn-junction devices. At voltages below 5V, high leak-
age current and junction capacitance render conven-
tional avalanche technology impractical for most
applications. However, by utilizing the EPD technology,
the SR2.8 can effectively operate at 2.8V while main-
taining excellent electrical characteristics.
The EPD TVS employs a complex nppn structure in
contrast to the pn structure normally found in tradi-
tional silicon-avalanche TVS diodes. The EPD mecha-
nism is achieved by engineering the center region of
the device such that the reverse biased junction does
not avalanche, but will “punch-through” to a conduct-
ing state. This structure results in a device with supe-
rior dc electrical parameters at low voltages while
maintaining the capability to absorb high transient
currents.
The IV characteristic curve of the EPD device is shown
in Figure 1. The device represents a high impedance
to the circuit up to the working voltage (V
). During a
transient event, the device will begin to conduct as it is
biased in the reverse direction. When the punch-
through voltage (V
) is exceeded, the device enters a
low impedance state, diverting the transient current
away from the protected circuit. When the device is
conducting current, it will exhibit a slight “snap-back” or
negative resistance characteristic due to its structure.
This must be considered when connecting the device
to a power supply rail. To return to a non-conducting
state, the current through the device must fall below
the snap-back current (approximately < 50mA).
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