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参数资料
| 型号： | SRM-622 |
| 厂商： | VECTRON INTERNATIONAL |
| 元件分类： | 数字传输电路 |
| 英文描述： | SONET/SDH Fiber-Optic Receiver Module with SAW Filter Clock Recovery and Data Retiming(SONET/SDH 光纤接收模块(带SAW滤波器,时钟恢复和数据重定时功能)) |
| 中文描述： | RECEIVER, DFO20 |
| 封装： | 1.300 X 0.635 INCH, MODULE, DIP-20 |
| 文件页数： | 4/8页 |
| 文件大小： | 181K |
| 代理商： | SRM-622 |
SRM-622 SONET/SDH Receiver Module
VI
603-598-0070
4
Performance Characteristics
Table 2. Electrical Performance
Parameter
Symbol
Minimum
Typical
Maximum
Units
Input Signal Rate
1
f
O
621.956
622.08
622.204
Mb/s
Operating Temperature
T
O
-40
+85
°C
Power Supply Voltage
V
CC
4.5
5.0
5.5
V
pin Detector Bias Voltage (pin10)
V
D
0
5.0
5.5
V
Power Supply Current
I
CC
300
mA
Data and Clock Output Levels
2
Low
High
V
OL
V
OH
V
CC
- 1.95
V
CC
- 1.03
V
CC
- 1.63
V
CC
- 0.88
V
V
Clock to Data Alignment
3
T
CDA
-100
+100
ps
Data and Clock Output Rise and Fall Times
4
T
R,
T
F
275
375
500
ps
Output Clock Duty Cycle
Duty
45
50
55
%
Received Power Level Flag
Decreasing Optical Power
Increasing Optical Power
LOS
-34
-31
dBm
dBm
Flag Hysteresis
Hyst
3
dB
Acquisition Time
5
T
A
2
μ
s
Output Clock Random Jitter
6
J
C
10
ps rms
1. Other center frequencies are available in the 124 to 622 MHz frequency range. Please contact VTI for further details.
2. Measured with a load of R
L
= 50
to V
CC
- 2 V. See figures 3 and 4. ECL levels are specified for dc measurement, an additional tolerance of 50 mV should be included for
dynamic measurements.
3. Alignment of clock and data outputs (see Figure 5.).
4. Measured at 20% to 80% levels.
5. Time required to achieve valid data and clock outputs with a transition density of at least 50%.
6. Measured with an input data pseudorandum word 2
- 1.
Figure 3. PECL Interface
+5 V
SRM-622
Clock
Clock
Data
Data
Flag
Flag
9
11
2.2
μ
F
0.1
μ
F
1
μ
H
82
82
82
82
2.2
μ
F
12
124
124
124
124
14
10
7
4
5
1k
+5 V
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