参数资料
型号: SRV08-4.TC
元件分类: TVS二极管 - 瞬态电压抑制
英文描述: 150 W, UNIDIRECTIONAL, SILICON, TVS DIODE
封装: PLASTIC PACKAGE-6
文件页数: 5/7页
文件大小: 497K
代理商: SRV08-4.TC
5
2002 Semtech Corp.
www.semtech.com
PROTECTION PRODUCTS
SRV08-4
PIN Descriptions
these devices virtually eliminate the disadvantages of
using discrete components to implement this topology.
Consider the situation shown in Figure 3 where dis-
crete diodes or diode arrays are configured for rail-to-
rail protection on a high speed line. During positive
duration ESD events, the top diode will be forward
biased when the voltage on the protected line exceeds
the reference voltage plus the V
F drop of the diode.
For negative events, the bottom diode will be biased
when the voltage exceeds the V
F of the diode.
At first
approximation, the clamping voltage due to the charac-
teristics of the protection diodes is given by:
V
C = VCC + VF
(for positive duration pulses)
V
C = -VF
(for negative duration pulses)
However, for fast rise time transient events, the
effects of parasitic inductance must also be consid-
ered as shown in Figure 4. Therefore, the actual
clamping voltage seen by the protected circuit will be:
V
C = VCC + VF + LP diESD/dt (for positive duration pulses)
V
C = -VF - LG diESD/dt
(for negative duration pulses)
ESD current reaches a peak amplitude of 30A in 1ns
for a level 4 ESD contact discharge per IEC 61000-4-2.
Therefore, the voltage overshoot due to 1nH of series
inductance is:
V = L
P diESD/dt = 1X10
-9
(30 / 1X10-9) = 30V
Example:
Consider a V
CC = 5V, a typical VF of 30V (at 30A) for the
steering diode and a series trace inductance of 10nH.
The clamping voltage seen by the protected IC for a
positive 8kV (30A) ESD pulse will be:
V
C = 5V + 30V + (10nH X 30V/nH) = 335V
Note that it is not uncommon for the V
F of discrete
diodes to exceed the damage threshold of the pro-
tected IC. This is due to the relatively small junction
area of typical discrete components. It is also possible
that the power dissipation capability of the discrete
diode will be exceeded, thus destroying the device.
The RailClamp is designed to overcome the inherent
disadvantages of using discrete signal diodes for ESD
suppression.
Figure 3 - “Rail-
Figure 3 - “Rail-TTTTTo-Rail” Pr
o-Rail” Pr
o-Rail” Proooootttttection T
ection T
ection Topology
opology
(First Approximation)
Figure 4 - The Effects of Parasitic Inductance
When Using Discrete Components to Implement
Rail-
Rail-TTTTTo-Rail Pr
o-Rail Pr
o-Rail Proooootttttection
ection
Applications Information (continued)
Figure 5 - Rail-
Figure 5 - Rail-TTTTTo-Rail Pr
o-Rail Pr
o-Rail Proooootttttection Using
ection Using
RailClam
RailClamp T
p T
p T VVVVVS Arra
S Arra
S Arrays
ys
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