参数资料
型号: SST25VF016B-50-4C-QAF-T
厂商: Microchip Technology
文件页数: 11/32页
文件大小: 0K
描述: IC FLASH SER 16M 50MHZ SPI 8WSON
标准包装: 2,000
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 16M(2M x 8)
速度: 50MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 8-WSON
供应商设备封装: 8-WSON
包装: 带卷 (TR)
16 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF016B
Data Sheet
High-Speed-Read (80 MHz)
The High-Speed-Read instruction supporting up to 80 MHz Read is initiated by executing an 8-bit com-
mand, 0BH, followed by address bits [A 23 -A 0 ] and a dummy byte. CE# must remain active low for the
duration of the High-Speed-Read cycle. See Figure 6 for the High-Speed-Read sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the speci-
fied address location. The data output stream is continuous through all addresses until terminated by a
low to high transition on CE#. The internal address pointer will automatically increment until the high-
est memory address is reached. Once the highest memory address is reached, the address pointer
will automatically increment to the beginning (wrap-around) of the address space. Once the data from
address location 1FFFFFH has been read, the next output will be from address location 000000H.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
SCK MODE 0
SI
0B
ADD.
ADD.
ADD.
X
MSB
MSB
SO
HIGH IMPEDANCE
N
D OUT
N+1
D OUT
N+2
D OUT
N+3
D OUT
N+4
D OUT
Note: X = Dummy Byte: 8 Clocks Input Dummy Cycle (V IL or V IH )
MSB
1271 HSRdSeq.0
Figure 6: High-Speed-Read Sequence
Byte-Program
The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected
byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction
applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE# must remain
active low for the duration of the Byte-Program instruction. The Byte-Program instruction is initiated by
executing an 8-bit command, 02H, followed by address bits [A 23 -A 0 ]. Following the address, the data is
input in order from MSB (bit 7) to LSB (bit 0). CE# must be driven high before the instruction is exe-
cuted. The user may poll the Busy bit in the software status register or wait T BP for the completion of
the internal self-timed Byte-Program operation. See Figure 7 for the Byte-Program sequence.
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39
SCK
MODE 0
SI
MSB
02
ADD.
MSB
ADD.
ADD.
D IN
MSB
LSB
SO
HIGH IMPEDANCE
1271 ByteProg.0
Figure 7: Byte-Program Sequence
?2011 Silicon Storage Technology, Inc.
11
DS25044A
08/11
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