参数资料
型号: SST25VF512-20-4C-SAE
厂商: Microchip Technology
文件页数: 9/29页
文件大小: 0K
描述: IC FLASH SER 512K 20MHZ 8SOIC
特色产品: SST Serial and Parallel Flash Memory
标准包装: 100
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 512K (64K x 8)
速度: 20MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 1452 (CN2011-ZH PDF)
512 Kbit SPI Serial Flash
A Microchip Technology Company
SST25VF512
Data Sheet
Instructions
Instructions are used to Read, Write (Erase and Program), and configure the SST25VF512. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or
Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list
of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of
CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE# must
be driven low before an instruction is entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high
transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the instruction
in progress and return the device to the standby mode. Instruction commands (Op Code), addresses,
and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions 1
Bus Cycle 2
1
2
3
4
5
Cycle
Type/Operation 3,4
S IN
S OUT
S IN
S OUT
S IN
S OUT
S IN
S OUT
S IN
S OUT
Read
Sector-Erase 5,6
Block-Erase 5,7
Chip-Erase 6
Byte-Program 6
Auto Address Increment
03H
20H
52H
60H
02H
AFH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
A 23 -A 16
A 23 -A 16
A 23 -A 16
-
A 23 -A 16
A 23 -A 16
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
A 15 -A 8
A 15 -A 8
A 15 -A 8
-
A 15 -A 8
A 15 -A 8
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
A 7 -A 0
A 7 -A 0
A 7 -A 0
-
A 7 -A 0
A 7 -A 0
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
X
-
-
-
D IN
D IN
D OUT
-
-
-
Hi-Z
Hi-Z
(AAI) Program 6,8
Read-Status-Register
05H
Hi-Z
X
D OUT
-
Note 9
-
Note 9
-
Note 9
(RDSR)
Enable-Write-Status-Reg-
50H
Hi-Z
-
-
-
-
-
-
-
-
ister (EWSR) 10
Write-Status-Register
01H
Hi-Z
Data
Hi-Z
-
-
-.
-
-
-
(WRSR) 10
Write-Enable (WREN)
Write-Disable (WRDI)
Read-ID
06H
04H
90H or
Hi-Z
Hi-Z
Hi-Z
-
-
00H
-
-
Hi-Z
-
-
00H
-
-
Hi-Z
-
-
ID
-
-
Hi-Z
-
-
X
-
-
D OUT12
ABH
Addr 11
T5.18 25076
1. A MS = Most Significant Address
A MS = A 15 for SST25VF512
Address bits above the most significant bit of each density can be V IL or V IH
2. One bus cycle is eight clock periods.
3. Operation: S IN = Serial In, S OUT = Serial Out
4. X = Dummy Input Cycles (V IL or V IH ); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use A MS -A 12 , remaining addresses can be V IL or V IH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable
(WREN) instruction must be executed.
7. Block addresses for: use A MS -A 15 , remaining addresses can be V IL or V IH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
?2011 Silicon Storage Technology, Inc.
9
DS25076A
10/11
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