参数资料
型号: SST25VF512A-33-4I-ZAE
厂商: Microchip Technology
文件页数: 17/28页
文件大小: 0K
描述: IC FLASH SER 512KB 33MHZ 8CSP
标准包装: 3,000
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 512K (64K x 8)
速度: 33MHz
接口: SPI 串行
电源电压: 2.7 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-UFBGA,CSPBGA
供应商设备封装: 8-CSP
包装: 管件
512 Kbit SPI Serial Flash
A Microchip Technology Company
SST25VF512A
Data Sheet
Write-Status-Register (WRSR)
The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register
(EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-
Status-Register instruction must be executed immediately after the execution of the Enable-Write-Sta-
tus-Register instruction (very next instruction bus cycle). This two-step instruction sequence of the
EWSR instruction followed by the WRSR instruction works like SDP (software data protection) com-
mand structure which prevents any accidental alteration of the status register values. The Write-Sta-
tus-Register instruction will be ignored when WP# is low and BPL bit is set to “1”. When the WP# is
low, the BPL bit can only be set from “0” to “1” to lock-down the status register, but cannot be reset
from “1” to “0”. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0,
and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP# pin is
driven high (V IH ) prior to the low-to-high transition of the CE# pin at the end of the WRSR instruction,
the BP0, BP1, and BPL bit in the status register can all be altered by the WRSR instruction. In this
case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as
altering the BP0 and BP1 bit at the same time. See Table 3 for a summary description of WP# and BPL
functions. CE# must be driven low before the command sequence of the WRSR instruction is entered
and driven high before the WRSR instruction is executed. See Figure 15 for EWSR and WRSR instruc-
tion sequences.
CE#
SCK
MODE 3
MODE 0
0 1 2 3 4 5 6 7
MODE 3
MODE 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
STATUS
REGISTER IN
SI
SO
MSB
50
01
MSB
HIGH IMPEDANCE
7 6 5 4 3 2 1 0
MSB
1264 F14.0
Figure 15: Enable-Write-Status-Register (EWSR) and Write-Status-Register (WRSR)
Sequence
?2011 Silicon Storage Technology, Inc.
17
DS25090A
10/11
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