参数资料
型号: SST25WF040-40-5I-SAF
厂商: Microchip Technology
文件页数: 11/36页
文件大小: 0K
描述: IC FLASH SER 4MB 40MHZ SPI 8SOIC
特色产品: SST Serial and Parallel Flash Memory
标准包装: 100
系列: SST25
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 4M (512K x 8)
速度: 40MHz
接口: SPI 串行
电源电压: 1.65 V ~ 1.95 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 1452 (CN2011-ZH PDF)
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit 1.8V SPI Serial Flash
A Microchip Technology Company
SST25WF512 / SST25WF010 / SST25WF020 / SST25WF040
Data Sheet
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25WF512/010/020/
040. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The
Write-Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment
(AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The
complete instructions are provided in Tables 9 and 10. All instructions are synchronized off a high-to-
low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signifi-
cant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 9: Device Operation Instructions for SST25WF512 and SST25WF010
Address
Dummy
Data
Maximum
Instruction
Description
Op Code Cycle 1
Cycle(s) 2 Cycle(s) Cycle(s) Frequency
Read
High-Speed Read
Read Memory
Read Memory at Higher
0000 0011b (03H)
0000 1011b (0BH)
3 0 1 to ?
3 1 1 to ?
20 MHz
Speed
4 KByte Sector-
Erase 4 KByte of
0010 0000b (20H)
3
0
0
Erase 3
memory array
32 KByte Block-
Erase 32 KByte block
0101 0010b (52H)
3
0
0
Erase 4
of memory array
Chip-Erase
Erase Full Memory Array 0110 0000b (60H)
0
0
0
or
1100 0111b (C7H)
Byte-Program
To Program One Data Byte 0000 0010b (02H)
3
0
1
AAI-Word-Pro-
Auto Address Increment
1010 1101b (ADH)
3
0
2 to ?
gram 5
Programming
RDSR 6
EWSR 7
Read-Status-Register
Enable-Write-Status-
0000 0101b (05H)
0110 0000b (50H)
0
0
0
0
1 to ?
0
WRSR
WREN 7
WRDI
RDID 8
Register
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H)
0
0
0
3
0
0
0
0
1
0
0
1 to ?
40 MHz
or
1010 1011b (ABH)
EBSY
Enable SO to output RY/ 0111 0000b (70H)
0
0
0
BY# status during AAI
programming
DBSY
Disable SO to output RY/ 1000 0000b (80H)
0
0
0
BY# status during AAI
programming
JEDEC-ID
JEDEC ID read 1001 1111b (9FH)
0
0
3 to ?
EHLD
Enable HOLD# pin func-
1010 1010b (AAH)
0
0
0
tionality of the RST#/
HOLD# pin
T9.0 25016
?2011 Silicon Storage Technology, Inc.
11
DS25016A
06/11
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