参数资料
型号: SST49LF016C-33-4C-NHE
厂商: Microchip Technology
文件页数: 12/43页
文件大小: 0K
描述: IC FLASH SER LPC 16MBIT 32PLCC
特色产品: SST Serial and Parallel Flash Memory
标准包装: 30
系列: SST49
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 16M(2M x 8)
速度: 33MHz
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 85°C
封装/外壳: 32-LCC(J 形引线)
供应商设备封装: 32-PLCC
包装: 管件
产品目录页面: 1453 (CN2011-ZH PDF)
16 Mbit LPC Serial Flash
A Microchip Technology Company
SST49LF016C
Data Sheet
Firmware Memory Cycles
Firmware Memory Read Cycle
Table 4: Firmware Memory Read Cycle Field Definitions
Field
Clock
Cycle
Field
Name
Contents
LAD[3:0] 1
LAD[3:0]
Direction Comments
1
START
1101
IN
LFRAME# must be active (low) for the part to respond. Only the last
start field (before LFRAME# transitions high) will be recognized. The
START field contents (1101b) indicate a Firmware Memory Read
cycle.
2
IDSEL
0000 to
1111
IN Indicates which SST49LF016C device should respond. If the
IDSEL (ID select) field matches the value of ID[3:0], then that par-
ticular device will respond to the LPC bus cycle.
3-9
MADD
R
YYYY
IN These seven clock cycles make up the 28-bit memory address.
YYYY is one nibble of the entire address. Addresses are trans-
ferred most-significant nibble first.
10
MSIZE
KKKK
IN The MSIZE field indicates how many bytes will be transferred dur-
ing multi-byte operations.
Device will execute multi-byte read of 2 MSIZE bytes. SST49LF016C
supports only MSIZE = 0, 1, 2, 4, 7 (1, 2, 4, 16, 128 Bytes), with
KKKK=0000b, 0001b, 0010b, 0100b, or 0111b.
11
TAR0
1111
IN,
In this clock cycle, the master has driven the bus to all ‘1’s and then
then Float floats the bus, prior to the next clock cycle. This is the first part of the
bus “turnaround cycle.”
12
TAR1
1111 (float)
Float,
The SST49LF016C takes control of the bus during this cycle.
then OUT
13
RSYN
C
0000
(READY)
OUT During this clock cycle, the device generates a “ready sync”
(RSYNC) indicating that the device has received the input data.
The least-significant nibble of the least-significant byte will be
available during the next clock cycle.
14-A
DATA
ZZZZ
OUT A=(13+2 n+1 ); n = MSIZE. Least significant nibbles outputs first.
(A+1)
TAR0
1111
OUT,
In this clock cycle, the SST49LF016C drives the bus to all ones
then Float and then floats the bus prior to the next clock cycle. This is the first
part of the bus “turnaround cycle.” A=(13+2 n+1 ); n = MSIZE
(A+2)
TAR1
1111 (float)
Float,
The host resumes control of the bus during this cycle.
then IN
A=(13+2 n+1 ); n = MSIZE
T4.0 25029
1. Field contents are valid on the rising edge of the present clock cycle.
LCLK
LFRAME#
Start
IDSEL
MADDR
MSIZE
TAR0
TAR1
RSYNC
DATA
LAD[3:0]
1101b 0000b A[27:24] A[23:20] A[19:16] A[15:12] A[11:8]
A[7:4]
A[3:0]
KKKKb
1111b
Tri-State 0000b
D 0 [3:0]
D 0 [7:4]
D n [3:0]
D n [7:4]
TAR
1237 F03.0
Figure 6: Firmware Memory Read Cycle Waveform
?2011 Silicon Storage Technology, Inc.
12
DS25029A
06/11
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