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参数资料
| 型号： | SST49LF080A-33-4C-NHE-T |
| 厂商： | Microchip Technology |
| 文件页数： | 8/50页 |
| 文件大小： | 0K |
| 描述： | IC FLASH SER LPC 8MBIT 32PLCC |
| 标准包装： | 750 |
| 系列： | SST49 |
| 格式 - 存储器： | 闪存 |
| 存储器类型： | FLASH |
| 存储容量： | 8M（1M x 8） |
| 速度： | 33MHz |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 32-LCC（J 形引线） |
| 供应商设备封装： | 32-PLCC |
| 包装： | 带卷 (TR) |
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8 Mbit LPC Flash
A Microchip Technology Company
SST49LF080A
Data Sheet
LPC Mode
Device Operation
The LPC mode uses a 5-signal communication interface, a 4-bit address/data bus, LAD[3:0], and a
control line, LFRAME#, to control operations of the SST49LF080A. Cycle type operations such as
Memory Read and Memory Write are defined in Intel Low Pin Count Interface Specification, Revision
1.0. JEDEC Standard SDP (Software Data Protection) Program and Erase commands sequences are
incorporated into the standard LPC memory cycles. See Figures 7 through 12 for command
sequences.
LPC signals are transmitted via the 4-bit Address/Data bus (LAD[3:0]), and follow a particular
sequence, depending on whether they are Read or Write operations. LPC memory Read and Write
cycle is defined in Tables 5 and 6.
Both LPC Read and Write operations start in a similar way as shown in Figures 5 and 6. The host
(which is the term used here to describe the device driving the memory) asserts LFRAME# for two or
more clocks and drives a start value on the LAD[3:0] bus.
At the beginning of an operation, the host may hold the LFRAME# active for several clock cycles, and
even change the Start value. The LAD[3:0] bus is latched every rising edge of the clock. On the cycle
in which LFRAME# goes inactive, the last latched value is taken as the Start value. CE# must be
asserted one cycle before the start cycle to select the SST49LF080A for Read and Write operations.
Once the SST49LF080A identifies the operation as valid (a start value of all zeros), it next expects a
nibble that indicates whether this is a memory Read or Write cycle. Once this is received, the device is
now ready for the Address cycles. The LPC protocol supports a 32-bit address phase. The
SST49LF080A encodes ID and register space access in the address field. See Table 3 for address bits
definition.
For Write operation the Data cycle will follow the Address cycle, and for Read operation TAR and
SYNC cycles occur between the Address and Data cycles. At the end of every operation, the control of
the bus must be returned to the host by a 2-clock TAR cycle.
Table 3: Address bits definition
A 31 : A 251
1111 111b or 0000 000b
A 24 :A 23
ID[3:2] 2
A 22
1 = Memory Access
A 21 : A 20
ID[1:0] 2
A 19 :A 0
Device Memory address
0 = Register access
T3.1 25026
1. The top 32MByte address range FFFF FFFFH to FE00 0000H and the bottom 128 KByte memory access address
000F FFFFH to 000E 0000H are decoded.
2. See Table 7 for multiple device selection configuration
?2011 Silicon Storage Technology, Inc.
8
DS25086A
11/11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SST49LF080A-33-4C-WH | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:8 Mbit LPC Flash |
| SST49LF080A-33-4C-WHE | 功能描述:闪存 1M X 8 33MHz RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST49LF080A-33-4C-WHE-T | 功能描述:闪存 3.0 to 3.6V 8Mbit LPC Firmware 闪存 RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST49LF160C | 制造商:SST 制造商全称:Silicon Storage Technology, Inc 功能描述:16 Mbit LPC Flash |
| SST49LF160C334CNHE | 制造商:Microchip Technology Inc 功能描述: |
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