参数资料
型号: SST49LF080A-33-4C-WHE-T
厂商: Microchip Technology
文件页数: 10/50页
文件大小: 0K
描述: IC FLASH SER LPC 8MBIT 32TSOP
标准包装: 1,500
系列: SST49
格式 - 存储器: 闪存
存储器类型: FLASH
存储容量: 8M(1M x 8)
速度: 33MHz
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: 0°C ~ 85°C
封装/外壳: 32-TFSOP(0.488",12.40mm 宽)
供应商设备封装: 32-TSOP
包装: 带卷 (TR)
8 Mbit LPC Flash
A Microchip Technology Company
INIT#, RST#
SST49LF080A
Data Sheet
A V IL on INIT# or RST# pin initiates a device reset. INIT# and RST# pins have the same function
internally. It is required to drive INIT# or RST# pins low during a system reset to ensure proper
CPU initialization. During a Read operation, driving INIT# or RST# pins low deselects the device
and places the output drivers, LAD[3:0], in a high-impedance state. The reset signal must be held
low for a minimal duration of time T RSTP . A reset latency will occur if a reset procedure is performed
during a Program or Erase operation. See Table 19, Reset Timing Parameters for more informa-
tion. A device reset during an active Program or Erase will abort the operation and memory con-
tents may become invalid due to data being altered or corrupted from an incomplete Erase or
Program operation.
System Memory Mapping
The LPC interface protocol has address length of 32-bit or 4 GByte. The SST49LF080A will
respond to addresses in the range as specified in Table 4.
Refer to “Multiple Device Selection” section for more detail on strapping multiple SST49LF080A
devices to increase memory densities in a system and “Registers” section on valid register
addresses.
Table 4: Address Decoding Range
ID Strapping
Device #0 - 3
Device #4 - 7
Device #8 - 11
Device #12 - 15
Device #0 1
Device Access
Memory Access
Register Access
Memory Access
Register Access
Memory Access
Register Access
Memory Access
Register Access
Memory Access
Address Range
FFFF FFFFH : FFC0 0000H
FFBF FFFFH : FF80 0000H
FF7F FFFFH : FF40 0000H
FF3F FFFFH : FF00 0000H
FEFF FFFFH : FEC0 0000H
FEBF FFFFH : FE80 0000H
FE7F FFFFH : FE40 0000H
FE3F FFFFH : FE00 0000H
000F FFFFH : 000E 0000H
Memory Size
4 MByte
4 MByte
4 MByte
4 MByte
4 MByte
4 MByte
4 MByte
4 MByte
128 KByte
T4.0 25026
1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot
Block) both at
system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H.
?2011 Silicon Storage Technology, Inc.
10
DS25086A
11/11
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