参数资料
型号: SST89V54RDA-33-C-QIF
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, QCC40
封装: ROHS COMPLIANT, MO-220IWJJD-5, WQFN-40
文件页数: 63/84页
文件大小: 1755K
代理商: SST89V54RDA-33-C-QIF
66
Data Sheet
FlashFlex MCU
SST89E54RD2A/RDA / SST89E58RD2A/RDA
SST89V54RD2A/RDA / SST89V58RD2A/RDA
2007 Silicon Storage Technology, Inc.
S71339-01-000
1/07
13.0 SYSTEM CLOCK AND CLOCK OPTIONS
13.1 Clock Input Options and Recom-
mended Capacitor Values for Oscillator
Shown in Figure 13-1 are the input and output of an inter-
nal inverting amplifier (XTAL1, XTAL2), which can be con-
figured for use as an on-chip oscillator.
When driving the device from an external clock source,
XTAL2 should be left disconnected and XTAL1 should be
driven.
At start-up, the external oscillator may encounter a higher
capacitive load at XTAL1 due to interaction between the
amplifier and its feedback capacitance. However, the
capacitance will not exceed 15 pF once the external signal
meets the VIL and VIH specifications.
Crystal manufacturer, supply voltage, and other factors
may cause circuit performance to differ from one applica-
tion to another. C1 and C2 should be adjusted appropri-
ately for each design. Table 13-1, shows the typical values
for C1 and C2 vs. crystal type for various frequencies
More specific information about on-chip oscillator design
can be found in the FlashFlex Oscillator Circuit Design
Considerations application note.
13.2 Clock Doubling Option
By default, the device runs at 12 clocks per machine cycle
(x1 mode). The device has a clock doubling option to
speed up to 6 clocks per machine cycle. Please refer to
Table 13-2 for detail.
Clock double mode can be enabled either via the external
host mode or the IAP mode. Please refer to Table 4-2 for
the IAP mode enabling commands (When set, the EDC#
bit in SFST register will indicate 6 clock mode.).
The clock double mode is only for doubling the inter-
nal system clock and the internal flash memory, i.e.
EA#=1. To access the external memory and the peripheral
devices, careful consideration must be taken. Also note
that the crystal output (XTAL2) will not be doubled.
FIGURE
13-1: Oscillator Characteristics
TABLE
13-1:Recommended Values for C1 and
C2 by Crystal Type
Crystal
C1 = C2
Quartz
20-30pF
Ceramic
40-50pF
T13-1.0 1339
TABLE
13-2: Clock Doubling Features
Device
Standard Mode (x1)
Clock Double Mode (x2)
Clocks per
Machine Cycle
Max. External Clock Frequency
(MHz)
Clocks per
Machine Cycle
Max. External Clock Frequency
(MHz)
SST89E5xRD2A/RDA
12
40
6
20
SST89V5xRD2A/RDA
12
33
6
16
T13-2.0 1339
1339 F32.0
XTAL2
XTAL1
VSS
C1
Using the On-Chip Oscillator
External Clock Drive
C2
XTAL2
XTAL1
VSS
External
Oscillator
Signal
NC
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