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参数资料
| 型号： | SSTUAF32868AHLF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/21页 |
| 文件大小： | 0K |
| 描述： | IC REGIST BUFF 25BIT DDR2 176BGA |
| 标准包装： | 208 |
| 逻辑类型： | 1:1、1:2 可配置寄存缓冲器 |
| 电源电压： | 1.7 V ~ 1.9 V |
| 位数： | 28 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 176-TFBGA |
| 供应商设备封装： | 176-CABGA（6x15） |
| 包装： | 托盘 |
ICSSSTUAF32868A
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
11
ICSSSTUAF32868A
7094/15
Terminal Functions
Terminal Name
Electrical
Characteristics
Description
GND
Ground Input
Ground
VDD
1.8V nominal
Power Supply Voltage
VREF
0.9V nominal
Input Reference Clock
CLK
Differential Input
Positive Master Clock Input
CLK
Differential Input
Negative Master Clock Input
C
LVCMOS Input
Configuration Control Inputs - Register A or Register B
RESET
LVCMOS Input
Asynchronous Reset Input. Resets registers and disables Vref data
and clock differential-input receivers.
CSGEN
LVCMOS Input
Chip select gate enable – When high, D1-D28 inputs will be latched
only when at least one chip select input is low during the rising edge
of the clock. When low, the D1-D28 inputs will be latched and
redriven on every rising edge of the clock.
D1 - D28
SSTL_18 Input
Data Input. Clocked in on the crossing of the rising edge of CLK
and the falling edge of CLK.
DCS0, DCS1
SSTL_18 Input
Chip select inputs – These pins initiate DRAM address/command
decodes, and as such at least one will be low when a valid
address/command is present. The Register can be programmed to
redrive all D inputs (CSGEN high) only when at least one chip select
input is low. If CSGEN, DCS0, and DCS1 inputs are high, D1-D28
inputs will be disabled.
DCKE0, DCKE1
SSTL_18 Input
The outputs of this register bit will not be suspended by the DCS0
and DCS1 controls
DODT0, DODT1
SSTL_18 Input
The outputs of this register bit will not be suspended by the DCS0
and DCS1 controls
PAR_IN
SSTL_18 Input
Parity Input arrives one cycle after corresponding data input
Q1 - Q28
1.8V CMOS
Data Outputs that are suspended by the DCS0 and DCS1 controls
QCS0, QCS1
1.8V CMOS
Data Output that will not be suspended by the DCS0 and DCS1
controls
QCKE0, QCKE1
1.8V CMOS
Data Output that will not be suspended by the DCS0 and DCS1
controls
QODT0, QODT1
1.8V CMOS
Data Output that will not be suspended by the DCS0 and DCS1
controls
QERR
Open Drain Output
Output Error bit, generated one cycle after the corresponding data
output
NC
No Connection
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SSTUAF32868AHLFT | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTUAF32868BHLF | 功能描述:IC REG BUFFER 28BIT DDR2 176BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTUAF32868BHLFT | 功能描述:IC REG BUFFER 28BIT DDR2 176BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTUAF32869AHLF | 功能描述:IC REGIST BUFF 25BIT DDR2 150BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTUAF32869AHLFT | 功能描述:IC REGIST BUFF 25BIT DDR2 150BGA RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:- 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
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