参数资料
型号: SSTUB32864AHLFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 11/12页
文件大小: 0K
描述: IC REGIST BUFF 25BIT DDR2 96-BGA
标准包装: 2,500
逻辑类型: 1:2 可配置寄存缓冲器
电源电压: 1.7 V ~ 1.9 V
位数: 25,14
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 96-LFBGA
供应商设备封装: 96-CABGA(13.5x5.5)
包装: 带卷 (TR)
ICSSSTUB32864A
Advance Information
1166—10/05/05
8
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
MIN
MAX
UNITS
fclock
Clock frequency
410
MHz
tW
1ns
tACT
10
ns
tINACT
15
ns
Setup time
DCS before CK, CK
↓,
CSR high; CSR before
CK, CK
↓, DCS high
0.6
ns
DCS before CK, CK
↓,
CSR Low
0.5
ns
DODT, DCKE and data
before CK, CK
0.5
ns
DCS, DODT, DCKE and
data after CK, CK
0.4
ns
PAR_IN after CK, CK
0.4
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
Pulse duration, CK, CK High or Low
Differential inputs active time (See notes 1 and 2)
Differential inputs inactive time (See notes 1 and 3)
Hold time
tSU
th
Notes:
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
Setup time
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
TYP
MAX
fmax
410
MHz
tPDM
1
CLK, CLK#
Q
1.1
1.5
ns
tPDMSS
2
CLK, CLK#
Q
1.6
tphl
RESET#
Q
3
ns
Notes: 1. Includes 350ps test-load transmission-line delay
2. Guaranteed by design, not 100% tested in production.
SYMBOL
VDD = 1.8V ±0.1V
UNITS
From
(Input)
To
(Output)
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
MIN
MAX
dV/dt_r
1
4
V/ns
dV/dt_f
1
4
V/ns
dV/dt_
1
1V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
VDD = 1.8V ± 0.1V
UNIT
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