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参数资料
| 型号： | SSTV16857EC |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 锁存器 |
| 英文描述： | POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA56 |
| 封装： | PLASTIC, VFBGA-56 |
| 文件页数： | 4/11页 |
| 文件大小： | 94K |
| 代理商： | SSTV16857EC |
Philips Semiconductors
Product data
SSTV16857
14-bit SSTL_2 registered driver
with differential clock inputs
2
2002 Jun 05
853-2224 28376
FEATURES
Stub-series terminated logic for 2.5 V V
DDQ (SSTL_2)
Optimized for DDR (Double Data Rate) SDRAM applications
Inputs compatible with JESD8–9 SSTL_2 specifications.
Flow-through architecture optimizes PCB layout
ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
Same form, fit, and function as SSTL16877
Full DDR 200/266 solution @ 2.5 V when used with PCKV857
See SSTV16856 for driver/buffer version with mode select.
Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages
DESCRIPTION
The SSTV16857 is a 14-bit SSTL_2 registered driver with differential
clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ
must not exceed VCC. Inputs are SSTL_2 type with VREF normally at
0.5*VDDQ. The outputs support class I which can be used for
standard stub-series applications or capacitive loads. Master reset
(RESET) asynchronously resets all registers to zero.
The SSTV16857 is intended to be incorporated into standard DIMM
(Dual In-Line Memory Module) designs defined by JEDEC, such as
DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules.
Different from traditional SDRAM, DDR SDRAM transfers data on
both clock edges (rising and falling), thus doubling the peak bus
bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of
266 MHz. The modules require between 23 and 27 registered
control and address lines, so two 14-bit wide devices will be used on
each module. The SSTV16857 is intended to be used for SSTL_2
input and output signals.
The device data inputs consist of differential receivers. One
differential input is tied to the input pin while the other is tied to a
reference input pad, which is shared by all inputs.
The clock input is fully differential to be compatible with DRAM
devices that are installed on the DIMM. However, since the control
inputs to the SDRAM change at only half the data rate, the device
must only change state on the positive transition of the CLK signal.
In order to be able to provide defined outputs from the device even
before a stable clock has been supplied, the device must support an
asynchronous input pin (reset), which when held to the LOW state
will assume that all registers are reset to the LOW state and all
outputs drive a LOW signal as well.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
VDDQ
Q5
Q6
Q9
Q10
D12
D11
D10
D9
D8
RESET
VREF
GND
VCC
CLK+
CLK–
D7
D6
D5
D4
D3
VCC
GND
D2
D1
21
22
23
24
25
26
27
28
VDDQ
Q14
D14
D13
GND
VCC
Q1
Q2
GND
Q3
Q4
GND
VDDQ
Q7
VDDQ
GND
Q8
VDDQ
GND
Q11
Q12
GND
Q13
SW00685
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay; CLK to Qn
CL = 30 pF; VDDQ = 2.5 V
2.4
ns
CI
Input capacitance
VCC = 2.5 V
2.9
pF
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DWG NUMBER
48-Pin Plastic TSSOP
0 to +70
°C
SSTV16857DGG
SOT362-1
48-Pin Plastic TSSOP (TVSOP)
0 to +70
°C
SSTV16857DGV
SOT480-1
56-Ball Plastic VFBGA
0 to +70
°C
SSTV16857EC
SOT702-1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SSTV16857EV | 功能描述:寄存器 14BIT 2.5V REG DRV W/DIFF RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTV16857EV,118 | 功能描述:寄存器 14BIT 2.5V REG DRIVER W/DIFF RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTV16857EV,151 | 功能描述:寄存器 14BIT 2.5V REG DRIVER W/DIFF RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTV16857EV,157 | 功能描述:寄存器 14BIT 2.5V REG DRIVER W/DIFF RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTV16857EV-S | 功能描述:寄存器 14BIT 2.5V REG DRV W/DIFF RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
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