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| 型号： | SSTV16859CGLF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/9页 |
| 文件大小： | 0K |
| 描述： | IC BUS DVR UNIV 13-26BIT 64TSSOP |
| 产品变化通告： | Product Discontinuation 09/Dec/2011 |
| 标准包装： | 28 |
| 系列： | 74SSTV |
| 逻辑类型： | 13 位至 26 位寄存缓冲器，带 SSTL_2 输入和输出 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 位数： | 13，26 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-TFSOP （0.240"，6.10mm 宽） |
| 供应商设备封装： | 64-TSSOP |
| 包装： | 管件 |
2
ICSSSTV16859C
0703A—10/15/02
General Description
Pin Configuration (64-Pin TSSOP)
The 13-bit-to-26-bit ICSSSTV16859C is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2
I/O levels, except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive
edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#,
an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16859C supports low-
power standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset
to the logic “Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that
RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during
power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held
at a logic “Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable
the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until
the input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
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Pin Configuration (56-Pin MLF2)
ICSSSTV16859C
DDR 13-Bit to 26-Bit Registered Buffer
TSD
IDT / ICS DDR 13-Bit to 26-Bit Registered Buffer
ICSSSTV16859C
2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SSTV16859CGLFT | 功能描述:IC BUS DVR UNIV 13-26BIT 64TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:74SSTV 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTV16859CKLF | 功能描述:IC BUS DVR UNIV 13-26BIT 56VFQFN RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:74SSTV 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTV16859CKLFT | 功能描述:IC BUS DVR UNIV 13-26BIT 56VFQFN RoHS:是 类别:集成电路 (IC) >> 逻辑 - 专用逻辑 系列:74SSTV 产品变化通告:Product Discontinuation 25/Apr/2012 标准包装:1,500 系列:74SSTV 逻辑类型:DDR 的寄存缓冲器 电源电压:2.3 V ~ 2.7 V 位数:14 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:48-TFSOP（0.240"，6.10mm 宽） 供应商设备封装:48-TSSOP 包装:带卷 (TR) |
| SSTV16859DGG | 功能描述:寄存器 2.5V 13-26BIT SSTL 2 REG BUFR RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| SSTV16859DGG,112 | 功能描述:寄存器 2.5V 13-26BIT SSTL 2 REG BUFR RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
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