参数资料
| 型号： | ST16C550CP40-F |
| 厂商： | Exar Corporation |
| 文件页数： | 7/35页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE UART |
| 标准包装： | 9 |
| 系列： | * |
| 其它名称： | 1016-1759 |
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ST16C550
15
Rev. 5.01
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7: Not used and set to “0”.
FIFO Control Register (FCR)
This register is used to enable the FIFO’s, clear the
FIFO’s, set the transmit/receive FIFO trigger levels,
and select the DMA mode. The DMA, and FIFO
modes are defined as follows:
DMA MODE:
See description and DMA tables on page 11.
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a “1” when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-3:
Logic 0 = Set DMA mode “0”. (normal default condi-
tion)
Logic 1 = Set DMA mode “1.”
Transmit operation in mode “0”:
When the ST16C550 is in the ST16C450 mode
(FIFO’s disabled, FCR bit-0 = logic 0) or in the FIFO
mode (FIFO’s enabled, FCR bit-0 = logic 1, FCR bit-
3 = logic 0) and when there are no characters in the
transmit FIFO or transmit holding register, the -
TXRDY pin will be a logic 0. Once active the -TXRDY
pin will go to a logic 1 after the first character is loaded
into the transmit holding register.
Receive operation in mode “0”:
When the ST16C550 is in mode “0” (FCR bit-0 = logic
0) or in the FIFO mode (FCR bit-0 = logic 1, FCR bit-
3 = logic 0) and there is at least one character in the
receive FIFO, the -RXRDY pin will be a logic 0. Once
active the -RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode “1”:
When the ST16C550 is in FIFO mode ( FCR bit-0 =
logic 1, FCR bit-3 = logic 1 ), the -TXRDY pin will be
a logic 1 when the transmit FIFO is completely full. It
will be a logic 0 if one or more FIFO locations are
empty.
Receive operation in mode “1”:
When the ST16C550 is in FIFO mode (FCR bit-0 =
logic 1, FCR bit-3 = logic 1) and the trigger level has
been reached, or a Receive Time Out has occurred,
the -RXRDY pin will go to a logic 0. Once activated, it
will go to a logic 1 after there are no more characters
in the FIFO.
FCR BIT 4-5: Not used.
FCR BIT 6-7: These bits are used to set the trigger level
for the receive FIFO interrupt.
An interrupt is generated when the number of characters
in the FIFO equals the programmed trigger level. How-
ever the FIFO will continue to be loaded until it is full.
BIT-7
BIT-6
RX FIFO trigger level
00
1
01
4
10
8
11
14
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C550CP40-F | 制造商:Exar Corporation 功能描述:IC UART INTERFACE 1.5Mbps 5.5V DIP-40 |
| ST16C550CQ-0A-EVB | 功能描述:界面开发工具 Supports C550 48 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| ST16C550CQ48 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C550CQ48-F | 功能描述:UART 接口集成电路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C550CQ48TR-F | 功能描述:UART 接口集成电路 UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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