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参数资料
| 型号： | ST16C550CP40 |
| 厂商： | Exar Corporation |
| 文件页数： | 6/35页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16BYTE 40PDIP |
| 产品变化通告： | Leaded UART, V&I Obsolescence 11/Apr/2011 |
| 标准包装： | 9 |
| 通道数： | 1，UART |
| FIFO's： | 16 字节 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 40-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 40-PDIP |
| 包装： | 管件 |
| 其它名称： | 1016-1422 |
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ST16C550
14
Rev. 5.01
Transmit and Receive Holding Register
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set (logic 0 = at least one byte in FIFO /
THR, logic 1= FIFO/THR empty).
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the ST16C550 and receive FIFO by
reading the RHR register. The receive section pro-
vides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal
receiver counter starts counting clocks at 16x clock
rate. After 7 1/2 clocks the start bit time should be
shifted to the center of the start bit. At this time the start
bit is sampled and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the
receiver from assembling a false character. Receiver
status codes will be posted in the LSR.
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the ST16C550 INT output
pin.
IER Vs Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
the receive interrupts and register status will reflect
the following:
A) The receive data available interrupts are issued to
the external CPU when the FIFO has reached the
programmed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
B) FIFO status will also be reflected in the user
accessible ISR register when the FIFO trigger level is
reached. Both the ISR register status bit and the
interrupt will be cleared when the FIFO drops below
the trigger level.
C) The data ready bit (LSR BIT-0) is set as soon as a
character is transferred from the shift register to the
receive FIFO. It is reset when the FIFO is empty.
IER Vs Receive/Transmit FIFO Polled Mode Op-
eration
When FCR BIT-0 equals a logic 1; resetting IER bits
0-3 enables the ST16C550 in the FIFO polled mode of
operation. Since the receiver and transmitter have
separate bits in the LSR either or both can be used in
the polled mode by selecting respective transmit or
receive control bit(s).
A) LSR BIT-0 will be a logic 1 as long as there is one
byte in the receive FIFO.
B) LSR BIT 1-4 will indicate if an overrun error
occurred.
C) LSR BIT-5 will indicate when the transmit FIFO is
empty.
D) LSR BIT-6 will indicate when both the transmit
FIFO and transmit shift register are empty.
E) LSR BIT-7 will indicate any FIFO data errors.
IER BIT-0:
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
Logic 1 = Enable the receiver ready interrupt.
IER BIT-1:
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt.
IER BIT-2:
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C550CP40-F | 功能描述:UART 接口集成电路 SINGLE UART W/16 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C550CP40-F | 制造商:Exar Corporation 功能描述:IC UART INTERFACE 1.5Mbps 5.5V DIP-40 |
| ST16C550CQ-0A-EVB | 功能描述:界面开发工具 Supports C550 48 ld TQFP, ISA Interface RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| ST16C550CQ48 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C550CQ48-F | 功能描述:UART 接口集成电路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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