参数资料
| 型号： | ST16C552CJ68TR-F |
| 厂商： | Exar Corporation |
| 文件页数： | 9/39页 |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 16B DUAL 68PLCC |
| 标准包装： | 250 |
| 特点： | * |
| 通道数： | 2，DUART |
| FIFO's： | 16 字节 |
| 规程： | 打印机 |
| 电源电压： | 2.97 V ~ 5.5 V |
| 带并行端口： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 68-LCC（J 形引线） |
| 供应商设备封装： | 68-PLCC |
| 包装： | 带卷 (TR) |
| 其它名称： | ST16C552CJ68TR-F-ND |
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17
ST16C552/552A
Rev. 3.40
A2 A1 A0
Register
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
[Default]
Note 5*
Printer Port Register Set: Note 3*
[X]
0
PR[00]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
[X]
0
PR[00]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
[X]
0
1
SR[4F]
-Busy
-ACK
PE
SLCT
Error
-IRQ
logic
State
“1”
[X]
0
1
IOSEL
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
[X]
1
0
COM[E0]
logic
-INTP
-SLCTIN
INIT
-Auto
-STROBE
“1”
Enable
FDXT
[X]
1
0
CON[00]
[X]
PD 0-7
-INTP
-SLCTIN
INIT
-Auto
-STROBE
IN/OUT
Enable
FDXT
Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.
Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.
Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the
interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.
Note 5* The value between the square brackets represents the register’s initialized HEX value, X =N/A.
MODEM (UART) REGISTER DESCRIPTIONS
Transmit (THR) and Receive (RHR) Holding Reg-
isters
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set (logic 0 = FIFO full, logic 1= at least
one FIFO location available).
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the 552/552A and receive FIFO by
reading the RHR register. The receive section pro-
vides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal
receiver counter starts counting clocks at the 16x
clock rate. After 7 1/2 clocks the start bit time should
be shifted to the center of the start bit. At this time the
start bit is sampled and if it is still a logic 0 it is
validated. Evaluating the start bit in this manner
prevents the receiver from assembling a false charac-
ter. Receiver status codes will be posted in the LSR.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C552IJ68 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C552IJ68-F | 功能描述:UART 接口集成电路 DUAL UART W/16BYTE FIFO&PARALELPRNTPORT RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C552IJ68TR-F | 功能描述:UART 接口集成电路 DUAL UART W/16BYTE FIFO&PARALELPRNTPORT RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C554 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO |
| ST16C554CJ-0A-EVB | 功能描述:界面开发工具 Supports C554D 68 ld PLCC, ISA Interface RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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