参数资料
型号: ST16C650AIJ44-F
厂商: Exar Corporation
文件页数: 21/50页
文件大小: 0K
描述: IC UART FIFO 32B 44PLCC
标准包装: 27
特点: *
通道数: 1,UART
FIFO's: 32 字节
规程: 打印机,RS232,RS422,RS485
电源电压: 2.9 V ~ 5.5 V
带并行端口:
带IrDA 编码器/解码器:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 管件
ST16C650A
28
2.90V TO 5.5V UART WITH 32-BYTE FIFO
REV. 5.0.3
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. SEE”DMA MODE” ON PAGE 10.
Logic 0 = DMA Mode disabled (default).
Logic 1 = DMA Mode enabled.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when
the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last re-load. Table 10 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1).
These 2 bits are used to set the trigger level for the receiver FIFO interrupt. Table 10 shows the complete
selections..
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION WITH AUTO RTS HYSTERESIS
BIT-7
BIT-6
BIT-5
BIT
-4
TRANSMIT INT
TRIGGER LEVEL
RECEIVE INT
TRIGGER LEVEL
AUTO RTS
DE-ASSERT
AUTO RTS
RE-ASSERT
0
1
0
1
0
1
0
1
0
1
0
1
16
8
24
30
8
16
24
28
16
24
28
0
8
16
24
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
WORD LENGTH
0
5 (default)
0
1
6
1
0
7
1
8
FCR
BIT-1
BIT-0
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