ST22L032, L064, L096, L128
4/7
The product has two execution modes. Java mode
is used when JavaCard 2.x byte codes are be-
ing executed. Native mode is used for long JavaC-
ard byte codes, Native methods and system
routines. The processor enters Java mode when a
dispatch (DISP) instruction is encountered. When
executing in Native mode, there are two privilege
levels, User and Supervisor. Some instructions
can only be executed in Supervisor mode.
Instructions are of variable length, from 1 to 4
bytes in Native mode.
Special instructions exist for single-cycle stack op-
erations, a frequent occurrence in Java code.
Short branches and conditional branches within a
1 KByte block or the entire 16-MByte instruction
space are supported. The product has four stages
of pipeline in Native mode: fetch, decode, execute
and write-back. In Java mode, there are five stag-
es of pipeline: byte code-fetch, byte code-decode,
decode, execute and write-back.
The CPU core has 16 32-bit general purpose reg-
isters, as well as special registers of variable
length.
The chip also features a very high performance
Asynchronous Serial Interface (ASI) to support
high speed serial communication protocols com-
patible with ISO 7816 standard.
It is manufactured using the highly reliable ST
CMOS EEPROM technology.
EMBEDDED SOFTWARE
The Hardware Software Interface (HSI) imple-
ments the Hardware abstraction layer. It consists
of C interfaces to the EEPROM memory and pe-
ripherals. The drivers are:
–
Non Volatile Memory
–
Asynchronous Serial Interface
–
Central Interrupt Controller
–
Timer
–
Random Number Generator
–
Clock Manager
–
Memory Protection Unit
–
Sensors
–
Security
Note:
–
The HSI driver software layer is a C-oriented
API allowing efficient and secureaccess to the
peripherals and Non Volatile Memory for
programming or erasing.
–
Only the OS and JavaCard Virtual Machine
(JVM) domains can access the HSI software
layer (In the following the term OS will refer to
the software layer that is directly interfaced to
the HSI).
CRYPTOGRAPHIC LIBRARY
ST proposes a complete set of firmware subrou-
tines to allow fast and easy implementation of
cryptographic protocols. These subroutines have
been optimized according to the ST22 core speci-
ficities and dedicated instructions. Security issues
have been addressed to provide state of the art
security. The whole library is located in a specific
ROM area access through a single entry point.
Following features are available through library:
I
ASYMMETRICAL ALGORITHMS:
–
Basic modular arithmetic for various
lengths including modular product for odd
modulus.
–
More elaborate functions (with separate
fast and secure versions) such as
exponentiation, RSA signatures and
verifications for modulo length up to 2048
bits long.
–
Full internal RSA key generation. This
guarantees that the secret key will never
be known outside the chip and will
contribute to the overall system security.
–
Long random number generation
–
SHA-1
I
SYMMETRICAL ALGORITHMS
–
DES, Triple DES
–
AES-128, 192, 256