参数资料
型号: ST6200CN6/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO16
封装: ROHS COMPLIANT, PLASTIC, SSOP-16
文件页数: 36/100页
文件大小: 3849K
代理商: ST6200CN6/XXX
ST6200C ST6201C ST6203C
40/100
Doc ID 4563 Rev 5
I/O PORTS (Cont’d)
7.5 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
DRx with x = A or B.
Address DRA: 0C0h - Read/Write
Address DRB: 0C1h - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D[7:0] Data register bits.
Reading the DR register returns either the DR reg-
ister latch content (pin configured as output) or the
digital value applied to the I/O pin (pin configured
as input).
Caution: In input mode, modifying this register will
modify the I/O port configuration (see Table 8).
Do not use the Single bit instructions on I/O port
data registers. See (Section 7.2.5).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
DDRx with x = A or B.
Address DDRA: 0C4h - Read/Write
Address DDRB: 0C5h - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = DD[7:0] Data direction register bits.
The DDR register gives the input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
ORx with x = A or B.
Address ORA: 0CCh - Read/Write
Address ORB: 0CDh - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = O[7:0] Option register bits.
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
selected.
Output mode:
0: Open drain output(with P-Buffer deactivated)
1: Push-pull Output
Input mode: See Table 8.
Each bit is set and cleared by software.
Caution: Modifying this register, will also modify
the I/O port configuration in input mode. (see Ta-
Table 10. I/O Port Register Map and Reset Values
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
7
0
O7
O6
O5
O4
O3
O2
O1
O0
Address
(Hex.)
Register
Label
7
6
5
4
3
2
1
0
Reset Value
of all I/O port registers
0
0C0h
DRA
MSB
LSB
0C1h
DRB
0C4h
DDRA
MSB
LSB
0C5h
DDRB
0CCh
ORA
MSB
LSB
0CDh
ORB
1
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