- 您现在的位置：买卖IC网 > PDF目录385870 > ST6228CN3 (意法半导体) CB 5C 5#16S PIN RECP WALL PDF资料下载
参数资料
| 型号： | ST6228CN3 |
| 厂商： | 意法半导体 |
| 英文描述： | CB 5C 5#16S PIN RECP WALL |
| 中文描述： | 8位单片机与微控制器/ D转换器，自动重加载定时器，UART的秘书长办公室，安全复位和28引脚封装 |
| 文件页数： | 57/84页 |
| 文件大小： | 561K |
| 代理商： | ST6228CN3 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页当前第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页
57/84
57
ST62T28C/E28C
SERIAL PERIPHERAL INTERFACE
(Cont’d)
After 8 clock pulses (D7..D0) the output Q4 of the
4-bit binary counter becomes low, disabling the
clock from the counter and the data/shift register.
Q4 enables the clock to generate an interrupt on
the 8thclock falling edge as long as noreset of the
counter (processor write into the 8-bit data/shift
register) takes place. After a processor reset the
interrupt is disabled. The interrupt is active when
writing data in the shift register and desactivated
when writing any data in the SPI Interrupt Disable
register.
The generation of an interrupt to the Core provides
information that new data is available (input mode)
or that transmission is completed (output mode),
allowing the Core to generate an acknowledge on
the 9th clock pulse (I C-bus).
The interrupt is initiated by a high to lowtransition,
and thereforeinterrupt options mustbe set accord-
ingly as defined in the interrupt section.
After power on reset, or after writing the data/shift
register, the counter is reset to zero and the clock
is enabled. In this condition the data shift register
is ready for reception. No start condition has to be
detected. Through the user software the Core may
pull down the Sin line (Acknowledge) and slow
down the SCL, as long as it is needed to carry out
data from the shift register.
I C-bus Master-Slave, Receiver-Transmitter
When pins Sin and Sout are externally connected
together it is possible to use the SPI as a receiver
as well as a transmitter. Through software routine
(by using bit-set and bit-reset on I/O line) a clock
can be generated allowing I C-bus to workin mas-
ter mode.
When implementing an I C-bus protocol, the start
condition can be detected by settingthe processor
into a wait for start condition by enabling the inter-
rupt of the I/O port used for the Sin line. This frees
the processor from polling the Sin and SCL lines.
After thetransmission/reception theprocessor has
to poll for the STOP condition.
In slave mode the user software can slow down
the SCLclock frequency bysimply putting the SCL
I/O line in output open-drain mode and writing a
zero into the corresponding data register bit.
As it is possible to directly read the Sin pin directly
through the port register, thesoftware can detect a
difference between internal dataand external data
(master mode). Similar conditioncan be applied to
the clock.
Three (Four) Wire Serial Bus
It is possible to use a single general purpose I/O
pin (withthe corresponding interrupt enabled) as a
chip enable pin. SCL acts as active or passive
clock pin, Sinas data in and Sout as data out (four
wire bus). Sin and Sout can be connected together
externally to implement three wire bus.
Note
:
When the SPI is not used, the three I/O lines (Sin,
SCL, Sout) can be used as normal I/O, with the fol-
lowing limitation: bit Sout cannot be used in open
drain mode as this enables the shift registeroutput
to the port.
It is recommended, in order to avoid spurious in-
terrupts from the SPI, to disable the SPI interrupt
(the default state after reset) i.e. no write must be
made to the 8-bit shift register. An explicit interrupt
disable may be made in software by a dummy
write to the SPI interrupt disable register.
SPI Data/Shift Register
Address: DDh - Read/Write (SDSR)
A write into this register enables SPI Interrupt after
8 clock pulses.
SPI Interrupt Disable Register
Address: DCh - Read/Write (SIDR)
A dummy write to this register disables SPI Inter-
rupt.
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
D7
D6
D5
D4
D3
D2
D1
D0
相关PDF资料 |
PDF描述 |
|---|---|
| ST6228CN6 | ER 5C 5#16S PIN RECP WALL |
| ST6391 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6392B1 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6393B1 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6395B1 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST6228CN3/XXX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| ST6228CN6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT MCUs WITH A/D CONVERTER, AUTO-RELOAD TIMER, UART, OSG, SAFE RESET AND 28-PIN PACKAGE |
| ST6228CN6/XXX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| ST622X | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-Bit Micros |
| ST622XC-KIT | 制造商:未知厂家 制造商全称:未知厂家 功能描述:STARTER KIT DATASHEET FOR ST620X. ST621X AND ST622X |
发布紧急采购，3分钟左右您将得到回复。