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参数资料
| 型号： | ST6235BQ1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP52 |
| 封装： | PLASTIC, QFP-52 |
| 文件页数： | 46/82页 |
| 文件大小： | 617K |
| 代理商： | ST6235BQ1/XXX |
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ST62T35B/E35B
CONTROL REGISTERS (Cont’d)
Status Control Register 3 (SCR3)
Address: E2h - Read/Write/Clear only
Bit 7 = CP2POL.
CP2 Edge Polarity Select.
CP2POL defines the polarity for triggering the
CP2 event.
A 0 defines the action on a falling edge on the CP2
input, a 1 on a rising edge.
Bit 6 = CP2IEN.
CP2 Interrupt Enable. The Cap-
ture 2 Interrupt is masked when this bit is 0. Set-
ting the bit to 1 enables the CP2 event flag
CP2FLG to set the ARTIMER interrupt.
Bit 5 = CP2FLG.
CP2 Interrupt Flag. When this bit
is 0, no CP2 event has occurred since the last
clear of this flag. If the bit is at 1, the first CP2
event and capture into CP has occurred.
This bit cannot be set by program, only cleared.
Bit 4 = CMPIEN.
Compare Int. Enable. The Com-
pare Interrupt is masked when this bit is 0.
Setting the bit to 1 enables the Compare flag
CMPFLG to set the ARTIMER interrupt.
Bit 3 = CMPFLG.
Compare Flag. When this bit is
0, no Masked-Compare True event has occurred
since the last clear of this flag. If the bit is at 1, a
Masked-Compare event has occurred.
This bit cannot be set by program, only cleared.
Bit 2 = ZEROIEN.
Compare to Zero Int Enable.
The Masked-Counter Zero Interrupt is masked
when this bit is 0. Setting the bit to 1 enables the
ZEROFLG flag to set the ARTIMER interrupt.
Bit 1 = ZEROFLG.
Compare to Zero Flag. When
this bit is 0, no Masked-Counter Zero event has
occurred since the last clear of this flag. If the bit is
at 1, a Masked-Counter Zero event has occurred
as the Masked Counter state equals 0 when run-
ning or on hold (not on Reset).
Bit 0 = PWMMD.
PWM Output Mode Control.The
PWM Output mode is set by this bit; when 0, the
PWM output is run in set/reset mode (the PWM
output is set on a Masked-Counter Zero event and
is reset when on a Masked-Compare event).
When 1 the PWM output is in toggle mode; PWM
toggles its state on every Masked-Compare event.
Notes:
A Masked-Compare is the logical AND of the
Mask Register MASK with the Counter Register
CT, compared with the logical AND of the com-
pare
Register
CMP:
[(MASK
&
CT)
=
(MASK&CMP)].
A Masked-Counter Zero is the logical AND of the
Mask Register MASK with the Counter Register
CT, compared with zero: [(MASK & CT) = 0000h]
70
CP2POL CP2IEN CP2FLG CMPIEN
CMFLG
ZEROIEN ZEROFLG PWMMD
49
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST6235BQ3 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART |
| ST6235BQ3/XXX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| ST6235BQ6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT OTP/EPROM MCUs WITH A/D CONVERTER, 16-BIT AUTO-RELOAD TIMER, EEPROM, SPI AND UART |
| ST6235BQ6/XXX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:8-Bit Microcontroller |
| ST623X | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8/16-Bit Micros |
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