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参数资料
| 型号： | ST62E35BG1 |
| 元件分类： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件页数： | 33/84页 |
| 文件大小： | 918K |
| 代理商： | ST62E35BG1 |
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ST62T53C/T60C/T63C ST62E60C
INTERRUPTS
(Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h
—
Write Only
Reset status: 00h
Bit 7, Bits 3-0 =
Unused
.
Bit 6 =
LES
:
Level/Edge Selection bit
.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Bit 5 =
ESB
:
Edge Selection bit
.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 =
GEN
:
Global Enable Interrupt
. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on these MCUs are
summarized in the
Table 9
with associated mask
bit to enable/disable the interrupt request.
Table 9Interrupt Requests and Mask Bits
7
0
-
LES
ESB
GEN
-
-
-
-
Peripheral
Register
Address
Register
C8h
D4h
D1h
Mask bit
Masked Interrupt Source
Interrupt
vector
GENERAL
TIMER
A/D CONVERTER
IOR
TSCR1
ADCR
GEN
ETI
EAI
OVIE
CPIE
EIE
SPIE
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
All Interrupts, excluding NM
I
TMZ: TIMER Overflow
EOC: End of Conversion
OVF: AR TIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
SPRUN: End of Transmission
PAn pin
PBn pin
PCn pin
Vector 4
Vector 4
AR TIMER
ARMC
D5h
Vector 3
SPI
Port PAn
Port PBn
Port PCn
SPIMOD
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
E2h
C0h-C4h
C1h-C5h
C2h-C6h
Vector 2
Vector 1
Vector 1
Vector 2
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