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参数资料
| 型号： | ST62P15CM3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, PDSO28 |
| 封装： | PLASTIC, SOP-28 |
| 文件页数： | 96/105页 |
| 文件大小： | 1412K |
| 代理商： | ST62P15CM3 |
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ST6215C/ST6225C
90/105
8-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
Notes:
1. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 1mA (assuming that the impedance of the analog voltage
is lower than the specified limits).
- Pure digital pins must have a negative injection less than 1mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
2. Data based on characterization results over the whole temperature range, monitored in production.
Figure 73. ADC Accuracy Characteristics
Note: ADC not present on some devices. See device summary on page 1.
Symbol
Parameter
Conditions
Min
Typ.
Max
Unit
|ET|
Total unadjusted error 1)
VDD=5V
2)
fOSC=8MHz
1.2
±2, fosc>1.2MHz
±4, fosc>32KHz
LSB
EO
Offset error 1)
0.72
EG
Gain Error 1)
-0.31
|ED|
Differential linearity error 1)
0.54
|EL|
Integral linearity error 1)
EO
EG
1LSBIDEAL
1LSB
IDE AL
V
DDA
V
SSA
–
256
-----------------------------------------
=
Vin (LSBIDEAL)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
Digital Result ADCDR
255
254
253
5
4
3
2
1
0
7
6
1234
567
253 254 255 256
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
1
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